公开(公告)号：US5961657A

公开(公告)日：1999-10-05

申请号：US770671

申请日：1996-12-20

申请人： Chan-Jong Park ,  Se-Jin Jeong

发明人： Chan-Jong Park ,  Se-Jin Jeong

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/26 ,  G11C29/34 ,  G11C29/38 ,  G06F11/00

CPC分类号： G11C29/38 ,  G11C29/26

摘要： There is disclosed a parallel test circuit for a semiconductor memory device having a memory army with a plurality of memory cells and a plurality of comparators used for high-speed memory cell test, including a plurality of fist comparators performing first comparison with respect to data transmitted through a plurality of data output lines formed near memory blocks of the memory array; a plurality of second comparators coupled in common with each output terminal of the first comparators and performing second comparison with respect to output data of the first comparators; a multiplexer multiplexing output of the second comparator; first and second switches alternatively connected to an output terminal of the multiplexer; and a data output buffer coupled in common with output terminals of the first and second switches and buffering outputs of the first and second switches. The multiplexer is connected to the first switches for a first mode operation, and is connected to the second switch for a second mode operation to thereby perform a two-way data test.

摘要翻译： 公开了一种用于半导体存储器件的并行测试电路，该半导体存储器具有具有多个存储器单元的存储器和用于高速存储器单元测试的多个比较器，包括多个第一比较器，其执行关于发送的数据的第一比较 通过形成在存储器阵列的存储块附近的多个数据输出线; 多个第二比较器，与第一比较器的每个输出端共同耦合，并对第一比较器的输出数据执行第二比较; 多路复用器多路复用第二比较器的输出; 交替地连接到多路复用器的输出端的第一和第二开关; 以及与第一和第二开关的输出端共同耦合的数据输出缓冲器，并缓冲第一和第二开关的输出。 复用器连接到第一开关用于第一模式操作，并且连接到第二开关用于第二模式操作，从而进行双向数据测试。

公开(公告)号：US5621679A

公开(公告)日：1997-04-15

申请号：US445784

申请日：1995-05-22

申请人： Dong-Il Seo ,  Se-Jin Jeong

发明人： Dong-Il Seo ,  Se-Jin Jeong

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  G11C5/06

CPC分类号： G11C7/1006 ,  G11C7/10

摘要： The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device and a method for arranging a signal line therein which can realize a high bandwidth by embodying a chip architecture being comprised of a multi I/O line. A semiconductor memory device includes arrays comprised of a plurality of reference blocks for storing a plurality of memory cells, a plurality of word lines extending in the direction of length of a chip, a plurality of bit lines extending in a vertical direction of length of a chip, each pair of bit lines being comprised of a bit line and a complementary bit line, a plurality of data I/O lines arranged on the upper portion of the arrays and extending in the vertical direction, each pair of data I/O lines being comprised of a data I/O line and a complementary data I/O line and being one by one connected to each pair of bit lines, and a plurality of column selection lines arranged in the vertical direction and adjacent to the data I/O line and complementary data I/O line, for controlling connection of each pair of bit lines to the data I/O lines.

摘要翻译： 半导体存储器件技术领域本发明涉及一种半导体存储器件，更具体地说，涉及一种半导体存储器件以及用于在其中布置信号线的方法，其中通过体现由多I / O线构成的芯片结构，可实现高带宽。 一种半导体存储器件，包括由用于存储多个存储器单元的多个参考块，沿芯片长度方向延伸的多个字线，沿着长度方向的垂直方向延伸的多个位线， 每对位线由位线和互补位线组成，多个数据I / O线布置在阵列的上部并在垂直方向上延伸，每对数据I / O线 由数据I / O线和互补数据I / O线构成，并且连接到每对位线，并且沿着垂直方向排列并与数据I / O相邻的多个列选择线 线和互补数据I / O线，用于控制每对位线到数据I / O线的连接。

公开(公告)号：US5783480A

公开(公告)日：1998-07-21

申请号：US580595

申请日：1995-12-29

申请人： Dong-Il Seo ,  Se-Jin Jeong

发明人： Dong-Il Seo ,  Se-Jin Jeong

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  H01L23/528

CPC分类号： G11C7/1006 ,  G11C7/10

摘要： A semiconductor memory device architecture and method thereof obtains a high data bandwidth by forming multiple input/output lines. A unit array has a plurality of reference blocks formed in a length direction of the device, each reference block storing a plurality of memory cells. A sub array has a plurality of unit arrays formed in a longitudinal direction perpendicular to the length direction. A word line selects memory cells from within the reference blocks, the word line extending in the length direction. A pair of bit lines and a pair of data input/output lines extend in the longitudinal direction. The pair of data input/output lines are correspondingly connected to 2.sup.n (n=1,2, . . . ) pairs of bit lines. A read select signal line selects a pair of bit lines from among 2.sup.n pairs of bit lines connected to one pair of data input/output lines in response to an input of a column address during a read operation. A write select signal line selects a pair of bit lines from among 2.sup.n pairs of bit lines connected to one pair of data input/output lines in response to an input of a column address during a write operation. A column gate connects the pair of bit lines to the pair of data input/output lines. A column select line extends in the longitudinal direction and controls the column gate, and a pair of main data input/output lines are connected correspondingly through a multiplexer to a plurality of data input/output lines.

摘要翻译： 半导体存储器件结构及其方法通过形成多个输入/输出线来获得高数据带宽。 单元阵列具有沿设备的长度方向形成的多个参考块，每个参考块存储多个存储单元。 子阵列具有沿垂直于长度方向的纵向方向形成的多个单元阵列。 字线从参考块内选择存储单元，字线在长度方向上延伸。 一对位线和一对数据输入/输出线在纵向方向上延伸。 该对数据输入/输出线对应地连接到2n（n = 1,2，...）位线。 读取选择信号线响应于在读取操作期间的列地址的输入，从连接到一对数据输入/输出线的2n对位线中选择一对位线。 写入选择信号线在写入操作期间响应于列地址的输入，从连接到一对数据输入/输出线的2n对位线中选择一对位线。 列栅极将该对位线连接到该对数据输入/输出线。 列选择线在纵向上延伸并且控制列门，并且一对主数据输入/输出线通过多路复用器相应地连接到多个数据输入/输出线。

公开(公告)号：US5677886A

公开(公告)日：1997-10-14

申请号：US558105

申请日：1995-11-13

申请人： Dong-Il Seo ,  Sei-Seung Yoon ,  Se-Jin Jeong

发明人： Dong-Il Seo ,  Sei-Seung Yoon ,  Se-Jin Jeong

IPC分类号： G11C11/417 ,  G11C7/06 ,  G11C7/12 ,  G11C11/407 ,  G11C11/409 ,  G11C11/4091 ,  G11C13/00

CPC分类号： G11C7/065 ,  G11C11/4091 ,  G11C7/12

摘要： There is provided in the present invention a signal generator which generates a bit line equalization signal and a signal generator which generates a sense amplifier equalization signal to control the bit line equalization circuit and the sense amplifier equalization circuit, respectively. The generated bit line equalization signal and sense amplifier equalization signal both have a voltage level that is at least about equal to, and preferably greater than, an external power supply voltage. The signals generated by these signal generators can thus be used by operating voltages which are much less than was previously possible.

摘要翻译： 在本发明中提供了一种产生位线均衡信号的信号发生器和产生读出放大器均衡信号以分别控制位线均衡电路和读出放大器均衡电路的信号发生器。 所产生的位线均衡信号和读出放大器均衡信号都具有至少等于并且优选地大于外部电源电压的电压电平。 因此，由这些信号发生器产生的信号可以通过比以前可能的操作电压小的操作来使用。

公开(公告)号：US5537346A

公开(公告)日：1996-07-16

申请号：US352090

申请日：1994-11-30

申请人： Dong-Il Seo ,  Se-Jin Jeong

发明人： Dong-Il Seo ,  Se-Jin Jeong

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  G11C5/02

CPC分类号： G11C7/1006 ,  G11C7/10

摘要： A semiconductor memory device architecture and method thereof obtains a high data bandwidth by forming multiple input/output lines. A unit array has a plurality of reference blocks formed in a length direction of the device, each reference block storing a plurality of memory cells. A sub array has a plurality of unit arrays formed in a longitudinal direction perpendicular to the length direction. A word line selects memory cells from within the reference blocks, the word line extending in the length direction. A pair of bit lines and a pair of data input/output lines extend in the longitudinal direction. The pair of data input/output lines are correspondingly connected to 2.sup.n (n=1,2, . . . ) pairs of bit lines. A read select signal line selects a pair of bit lines from among 2.sup.n pairs of bit lines connected to one pair of data input/output lines in response to an input of a column address during a read operation. A write select signal line selects a pair of bit lines from among 2.sup.n pairs of bit lines connected to one pair of data input/output lines in response to an input of a column address during a write operation. A column gate connects the pair of bit lines to the pair of data input/output lines. A column select line extends in the longitudinal direction and controls the column gate, and a pair of main data input/output lines are connected correspondingly through a multiplexer to a plurality of data input/output lines.

摘要翻译： 半导体存储器件结构及其方法通过形成多个输入/输出线来获得高数据带宽。 单元阵列具有沿设备的长度方向形成的多个参考块，每个参考块存储多个存储单元。 子阵列具有沿垂直于长度方向的纵向方向形成的多个单元阵列。 字线从参考块内选择存储单元，字线在长度方向上延伸。 一对位线和一对数据输入/输出线在纵向方向上延伸。 该对数据输入/输出线对应地连接到2n（n = 1,2，...）位线。 读取选择信号线响应于在读取操作期间的列地址的输入，从连接到一对数据输入/输出线的2n对位线中选择一对位线。 写入选择信号线在写入操作期间响应于列地址的输入，从连接到一对数据输入/输出线的2n对位线中选择一对位线。 列栅极将该对位线连接到该对数据输入/输出线。 列选择线在纵向上延伸并且控制列门，并且一对主数据输入/输出线通过多路复用器相应地连接到多个数据输入/输出线。