公开(公告)号：US10065839B2

公开(公告)日：2018-09-04

申请号：US14370718

申请日：2012-01-06

申请人： Chan-Jong Park

发明人： Chan-Jong Park

IPC分类号： B66B23/20 ,  B66B23/16 ,  B66B23/04 ,  B66B21/02 ,  B66B23/06 ,  B66B23/24 ,  B66B23/02

摘要： A system for braking an escalator or moving walkway includes a handrail and passenger support in registration with one another so as to move together. A braking tensioner selectively increases tension in the handrail during operation. The increased tension serves to frictionally brake the handrail and hence the passenger support. The braking tensioner may be located in any of various locations depending upon system design, and may be driven in any suitable manner, e.g., hydraulically, electrically, electromagnetically, and so on. Frictional wear on the handrail is reduced by the fact that the described braking system spreads the frictional load over a large area of the handrail, e.g., the many locations where the handrail contacts the underlying support throughout its length.

公开(公告)号：US5961657A

公开(公告)日：1999-10-05

申请号：US770671

申请日：1996-12-20

申请人： Chan-Jong Park ,  Se-Jin Jeong

发明人： Chan-Jong Park ,  Se-Jin Jeong

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/26 ,  G11C29/34 ,  G11C29/38 ,  G06F11/00

CPC分类号： G11C29/38 ,  G11C29/26

摘要： There is disclosed a parallel test circuit for a semiconductor memory device having a memory army with a plurality of memory cells and a plurality of comparators used for high-speed memory cell test, including a plurality of fist comparators performing first comparison with respect to data transmitted through a plurality of data output lines formed near memory blocks of the memory array; a plurality of second comparators coupled in common with each output terminal of the first comparators and performing second comparison with respect to output data of the first comparators; a multiplexer multiplexing output of the second comparator; first and second switches alternatively connected to an output terminal of the multiplexer; and a data output buffer coupled in common with output terminals of the first and second switches and buffering outputs of the first and second switches. The multiplexer is connected to the first switches for a first mode operation, and is connected to the second switch for a second mode operation to thereby perform a two-way data test.

摘要翻译： 公开了一种用于半导体存储器件的并行测试电路，该半导体存储器具有具有多个存储器单元的存储器和用于高速存储器单元测试的多个比较器，包括多个第一比较器，其执行关于发送的数据的第一比较 通过形成在存储器阵列的存储块附近的多个数据输出线; 多个第二比较器，与第一比较器的每个输出端共同耦合，并对第一比较器的输出数据执行第二比较; 多路复用器多路复用第二比较器的输出; 交替地连接到多路复用器的输出端的第一和第二开关; 以及与第一和第二开关的输出端共同耦合的数据输出缓冲器，并缓冲第一和第二开关的输出。 复用器连接到第一开关用于第一模式操作，并且连接到第二开关用于第二模式操作，从而进行双向数据测试。

公开(公告)号：US5608677A

公开(公告)日：1997-03-04

申请号：US579913

申请日：1995-12-28

申请人： Sei-Seung Yoon ,  Chan-Jong Park ,  Byung-Chul Kim

发明人： Sei-Seung Yoon ,  Chan-Jong Park ,  Byung-Chul Kim

IPC分类号： G11C5/14 ,  G11C7/00

CPC分类号： G11C5/145

摘要： A voltage boosting circuit for a semiconductor memory device has a clock generator for supplying a chip master clock determining an active state and a stand-by state in respective response to first and second states thereof, for generating a detector control signal a first delay time after the first state of the chip master clock is generated, and for generating a latch control signal a second delay time after the first state of the chip master clock is generated. A boosting voltage detector responds to the detector control signal and the latch control signal to generate a detecting signal indicative of a current state of a boosting voltage potential. First and second boosting voltage generators generate the boosting voltage potential, respectively operating in the stand-by state and active state in accordance with the detecting signal and delayed chip master clock signal.

摘要翻译： 一种用于半导体存储器件的升压电路具有一个时钟发生器，用于在分别响应于其第一和第二状态提供确定有效状态和待机状态的芯片主时钟，以产生检测器控制信号，该第一延迟时间在 产生芯片主时钟的第一状态，并且用于在产生芯片主时钟的第一状态之后产生锁存控制信号第二延迟时间。 升压电压检测器响应于检测器控制信号和锁存控制信号，以产生指示升压电压电位的当前状态的检测信号。 第一和第二升压电压发生器根据检测信号和延迟芯片主时钟信号产生升压电压，分别工作在待机状态和有效状态。

公开(公告)号：US20150375968A1

公开(公告)日：2015-12-31

申请号：US14409269

申请日：2012-07-10

申请人： Chan-Jong Park ,  Alexander Turek

发明人： Chan-Jong Park ,  Alexander Turek

IPC分类号： B66B23/02

CPC分类号： B66B23/028 ,  B65G23/16

摘要： A drive chain band for a chain drive device having chain links and pins is provided. The drive chain band may include one or more drive bands, and a plurality of connectors disposed on the one or more drive bands. Each connector may have a toothed profile configured to directly receive and engage the pins.

摘要翻译： 提供了一种具有链条和销钉的链条驱动装置的驱动链带。 驱动链带可以包括一个或多个驱动带，以及设置在一个或多个驱动带上的多个连接器。 每个连接器可以具有构造成直接接收和接合销的齿形轮廓。

公开(公告)号：US07621389B2

公开(公告)日：2009-11-24

申请号：US11722830

申请日：2005-12-21

申请人： Chan Jong Park

发明人： Chan Jong Park

IPC分类号： B66B23/22

CPC分类号： B66B23/20

摘要： A curvature-adjustable handrail length compensation device for an escalator or a moving walkway is provided. The device comprises a frame, handrail support mounted along a length of the frame, and springs mounted to the frame to elastically support the handrail support. Each handrail support includes a supporting rod movably mounted through the frame, a first supporting roller mounted to an end of the supporting rod to support the handrail, and a stopper formed at the other end of the supporting rod. The spring is provided between the frame and the first supporting roller, and biases the first supporting roller away from the frame.

摘要翻译： 提供了一种用于自动扶梯或移动人行道的曲率可调的扶手长度补偿装置。 该装置包括沿着框架的长度安装的框架，扶手支撑件和安装到框架上以弹性地支撑扶手支撑件的弹簧。 每个扶手支撑件包括可移动地安装穿过框架的支撑杆，安装到支撑杆的端部以支撑扶手的第一支撑辊以及形成在支撑杆的另一端的止动件。 弹簧设置在框架和第一支撑辊之间，并且将第一支撑辊偏压离开框架。

公开(公告)号：US06313670B1

公开(公告)日：2001-11-06

申请号：US09433099

申请日：1999-11-03

申请人： Ki-whan Song ,  Chan-jong Park

发明人： Ki-whan Song ,  Chan-jong Park

IPC分类号： H03K300

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1069

摘要： A current control circuit capable of minimizing changes in an output high voltage VOH and an output low voltage VOL and quickly and accurately bringing a divided voltage to a steady state, and a packet-type semiconductor memory device including the current control circuit. The current control circuit includes a first differential amplification type buffer for transmitting the voltage of a first pad, that is, the output high voltage VOH, without change in response to a current control enable signal, a second differential amplification type buffer for transmitting the voltage of a second pad, that is, the output low voltage VOL, without change in response to the current control enable signal, and a voltage divider for dividing a voltage ranging between the voltage outputs of the first and second differential amplification buffers, and outputting the divided voltage. Accordingly, in the packet-type semiconductor memory device including the current control circuit, the current control circuit minimizes changes in the output high voltage VOH and the output low voltage VOL and quickly and accurately brings a divided voltage to a steady state, so that the current driving capability of an output driver for driving the second pad can be quickly controlled.

摘要翻译： 一种电流控制电路，其能够使输出高电压VOH和输出低电压VOL的变化最小化，并将分压后的电压快速准确地设定为稳定状态，以及包括电流控制电路的分组型半导体存储器件。 电流控制电路包括：第一差分放大型缓冲器，用于传输第一焊盘的电压，即输出高电压VOH，而不改变响应于电流控制使能信号;第二差分放大型缓冲器，用于传输电压 的第二焊盘，即输出低电压VOL，而不响应于电流控制使能信号而变化;以及分压器，用于分压第一和第二差分放大缓冲器的电压输出之间的电压范围，并输出 分压。 因此，在包括电流控制电路的分组型半导体存储器件中，电流控制电路使输出高电压VOH和输出低电压VOL的变化最小化，并且将分压后的电压快速准确地导入稳定状态， 可以快速地控制用于驱动第二焊盘的输出驱动器的电流驱动能力。

公开(公告)号：US6149435A

公开(公告)日：2000-11-21

申请号：US220422

申请日：1998-12-24

申请人： Chan Jong Park ,  Jin Sung Choi ,  Man Kyu Sung ,  Ji Hyung Lee ,  Sang Won Kim ,  Dong Hyun Kim ,  Jung Kak Kim ,  Chan Su Lee

发明人： Chan Jong Park ,  Jin Sung Choi ,  Man Kyu Sung ,  Ji Hyung Lee ,  Sang Won Kim ,  Dong Hyun Kim ,  Jung Kak Kim ,  Chan Su Lee

IPC分类号： G09B9/48 ,  G09B19/16 ,  G09B9/08

CPC分类号： G09B9/48 ,  G09B19/165

摘要： The present invention is related to a system which is portable and attache the body of a trainee so that the trainee can practice navigating of a model airplane at an arbitrary location, contrary to the system of a large-sized airplane. According to an object of the present invention there is provided a trainee navigates a model airplane virtually by simulating a model airplane using a computer by combining the three-dimensional virtual image of a model airplane and the actual image of the training site by a computer. The simulation method of a radio-controlled model airplane of the present invention is comprising the steps of recording various airplane models into the computer system; simulating the airplane model by processing signals received from the controller; producing images by rendering the results of signal processing of the simulation step; showing images which are to appear in two eyes of the user at both indicators of HMD(head-mounted display) or STHMD(see-through head-mounted display) in order to convert produced images to be three-dimensional; and producing the unique sound of the corresponding airplane model in three dimensions and listening the sound to the headphone of HMD or STHMD.

摘要翻译： 本发明涉及一种便携式并附着在受训者的身体上的系统，使得受训者可以在与大型飞机的系统相反的任意位置上练习驾驶模型飞机。 根据本发明的一个目的，提供一种受训者通过使用计算机通过模拟飞机的三维虚像和计算机的训练场的实际图像来模拟模型飞机来虚拟地导航模型飞机。 本发明的无线电控制模型飞机的模拟方法包括以下步骤：将各种飞机模型记录到计算机系统中; 通过处理从控制器接收的信号来模拟飞机模型; 通过渲染模拟步骤的信号处理结果产生图像; 显示在HMD（头戴式显示器）或STHMD（透视头戴式显示器）的两个指示器处出现在用户的两只眼睛中的图像，以便将生成的图像转换成三维; 并在三维空间中产生相应飞机模型的独特声音，并听取HMD或STHMD耳机的声音。

公开(公告)号：US5818266A

公开(公告)日：1998-10-06

申请号：US725737

申请日：1996-10-04

申请人： Chan-Jong Park

发明人： Chan-Jong Park

IPC分类号： H03K19/0175 ,  G11C7/10 ,  G11C11/407 ,  G11C7/00

CPC分类号： G11C7/1057 ,  G11C7/1051

摘要： A fast data transmission circuit for a semiconductor memory minimizes voltage variations of a data transmission line without the use of a separate data transmission voltage. The data transmission circuit includes a pair of input nodes, a data transmission line pair, a pair of sensing nodes, a pair of output nodes, and a control electrode. Prior to data transmission, the output nodes are pulled up to a high voltage state, the data transmission line pair is pulled down to a low voltage state, and the sensing nodes are held between the high and low voltage states. When the control pulse is applied to the control electrode, the sensing node voltage levels are transferred to the data transmission line pair by the sensing voltage transfer circuit. When one input node is pulled to a low voltage state, a corresponding one voltage level on one transmission line is changed, causing a corresponding change of voltage at one of the sensing nodes. The voltage difference at the sensing nodes causes a corresponding one of the output nodes to go to a low voltage state while the other output node remains at the high voltage state.

摘要翻译： 用于半导体存储器的快速数据传输电路使数据传输线的电压变化最小化，而不使用单独的数据传输电压。 数据传输电路包括一对输入节点，数据传输线对，一对感测节点，一对输出节点和控制电极。 在数据传输之前，输出节点被拉高至高电压状态，数据传输线对被拉低至低电压状态，感测节点保持在高电压状态和低电压状态之间。 当控制脉冲施加到控制电极时，感测电压电平通过感测电压传输电路传送到数据传输线对。 当一个输入节点被拉至低电压状态时，一条传输线上相应的一个电压电平发生变化，导致感测节点之一处的相应的电压变化。 感测节点处的电压差导致相应的一个输出节点进入低电压状态，而另一个输出节点保持在高电压状态。

公开(公告)号：US06285573B1

公开(公告)日：2001-09-04

申请号：US09514744

申请日：2000-02-28

申请人： Chan-jong Park

发明人： Chan-jong Park

IPC分类号： G11C702

CPC分类号： G11C11/4074 ,  G11C5/063

摘要： A semiconductor integrated circuit includes a plurality of signal wires and an array of capacitor-based memory cells. The capacitors of the memory cells are electrically coupled to a common voltage source node where a voltage source provides supply power to the array. Shield wires positioned proximal to the signal wires are electrically coupled to the common voltage source node. A shield capacitor may be provided between the signal wires and the common voltage source node to provide further noise suppression.

摘要翻译： 半导体集成电路包括多个信号线和基于电容器的存储单元的阵列。 存储单元的电容器电耦合到公共电压源节点，其中电压源为阵列提供电力。 位于信号线附近的屏蔽线电耦合到公共电压源节点。 可以在信号线和公共电压源节点之间设置屏蔽电容器，以提供进一步的噪声抑制。

公开(公告)号：US5896324A

公开(公告)日：1999-04-20

申请号：US862828

申请日：1997-05-23

申请人： Tae-sung Jang ,  Chan-jong Park

发明人： Tae-sung Jang ,  Chan-jong Park

IPC分类号： G01R31/28 ,  G01R19/165 ,  G01R31/26 ,  G01R31/317 ,  G01R31/3185 ,  G11C5/14 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/14 ,  G11C16/04

CPC分类号： G11C5/143 ,  G01R31/31701

摘要： A method for detecting an overvoltage signal applied to a semiconductor memory device address pin reduces stress on the device and simplifies the testing process by dividing the voltage of the overvoltage signal and comparing it to a reference voltage, thereby generating a difference signal. The difference signal is buffered by a drive stage which generates a test mode output signal that places the memory device in a test mode. An overvoltage detection circuit for implementing this method includes a comparison signal generator having a resistive voltage divider for dividing the overvoltage signal and generating a comparison signal. A differential amplifier compares the comparison signal to a reference signal from a reference signal generator. The differential amplifier generates a difference signal which is coupled to a drive stage which generates a test mode output signal. The comparison signal generator, the differential amplifier, and the drive stage can be enabled in response to a test mode enable signal.

摘要翻译： 用于检测施加到半导体存储器件地址引脚的过电压信号的方法减少了器件上的应力，并且通过分压过电压信号的电压并将其与参考电压进行比较来简化测试过程，由此产生差分信号。 差分信号由驱动级缓冲，驱动级产生测试模式输出信号，使存储器件处于测试模式。 用于实现该方法的过电压检测电路包括具有用于分压过电压信号并产生比较信号的电阻分压器的比较信号发生器。 差分放大器将比较信号与参考信号发生器的参考信号进行比较。 差分放大器产生耦合到产生测试模式输出信号的驱动级的差信号。 可以响应于测试模式使能信号使能比较信号发生器，差分放大器和驱动级。