公开(公告)号：US08735238B2

公开(公告)日：2014-05-27

申请号：US13039525

申请日：2011-03-03

申请人： ChanSam Chang ,  Shigenobu Maeda ,  HeonJong Shin ,  ChangBong Oh

发明人： ChanSam Chang ,  Shigenobu Maeda ,  HeonJong Shin ,  ChangBong Oh

IPC分类号： H01L21/8238

CPC分类号： H01L29/0847 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/0692 ,  H01L29/1079 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

摘要： Methods and devices for forming both high-voltage and low-voltage transistors on a common substrate using a reduced number of processing steps are disclosed. An exemplary method includes forming at least a first high-voltage transistor well and a first low-voltage transistor well on a common substrate separated by an isolation structure extending a first depth into the substrate, using a first mask and first implantation process to simultaneously implant a doping material of a first conductivity type into a channel region of the low-voltage transistor well and a drain region for the high-voltage transistor well.

摘要翻译： 公开了使用减少数量的处理步骤在公共基板上形成高压和低压晶体管的方法和装置。 一种示例性方法包括使用第一掩模和第一注入工艺同时注入在至少第一高电压晶体管阱和第一低电压晶体管阱上形成阱，所述公共衬底由隔离结构隔开，所述隔离结构将第一深度延伸到衬底中 第一导电类型的掺杂材料进入低压晶体管阱的沟道区域和用于高压晶体管阱的漏极区域。

公开(公告)号：US07923805B2

公开(公告)日：2011-04-12

申请号：US11523068

申请日：2006-09-19

申请人： ChanSam Chang ,  Shigenobu Maeda ,  HeonJong Shin ,  ChangBong Oh

发明人： ChanSam Chang ,  Shigenobu Maeda ,  HeonJong Shin ,  ChangBong Oh

IPC分类号： H01L29/00

CPC分类号： H01L29/0847 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/0692 ,  H01L29/1079 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

摘要： Methods and devices for forming both high-voltage and low-voltage transistors on a common substrate using a reduced number of processing steps are disclosed. An exemplary method includes forming at least a first high-voltage transistor well and a first low-voltage transistor well on a common substrate separated by an isolation structure extending a first depth into the substrate, using a first mask and first implantation process to simultaneously implant a doping material of a first conductivity type into a channel region of the low-voltage transistor well and a drain region for the high-voltage transistor well.

摘要翻译： 公开了使用减少数量的处理步骤在公共基板上形成高压和低压晶体管的方法和装置。 一种示例性方法包括使用第一掩模和第一注入工艺同时注入在至少第一高电压晶体管阱和第一低电压晶体管阱上形成阱，所述公共衬底由隔离结构隔开，所述隔离结构将第一深度延伸到衬底中 第一导电类型的掺杂材料进入低压晶体管阱的沟道区域和用于高压晶体管阱的漏极区域。

公开(公告)号：US20070138592A1

公开(公告)日：2007-06-21

申请号：US11523068

申请日：2006-09-19

申请人： ChanSam Chang ,  Shigenobu Maeda ,  HeonJong Shin ,  ChangBong Oh

发明人： ChanSam Chang ,  Shigenobu Maeda ,  HeonJong Shin ,  ChangBong Oh

IPC分类号： H01L29/00

CPC分类号： H01L29/0847 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/0692 ,  H01L29/1079 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

摘要： Methods and devices for forming both high-voltage and low-voltage transistors on a common substrate using a reduced number of processing steps are disclosed. An exemplary method includes forming at least a first high-voltage transistor well and a first low-voltage transistor well on a common substrate separated by an isolation structure extending a first depth into the substrate, using a first mask and first implantation process to simultaneously implant a doping material of a first conductivity type into a channel region of the low-voltage transistor well and a drain region for the high-voltage transistor well.

摘要翻译： 公开了使用减少数量的处理步骤在公共基板上形成高压和低压晶体管的方法和装置。 一种示例性方法包括使用第一掩模和第一注入工艺同时注入在至少第一高电压晶体管阱和第一低电压晶体管阱上形成阱，所述公共衬底由隔离结构隔开，所述隔离结构将第一深度延伸到衬底中 第一导电类型的掺杂材料进入低压晶体管阱的沟道区域和用于高压晶体管阱的漏极区域。

公开(公告)号：US20150214341A1

公开(公告)日：2015-07-30

申请号：US14600689

申请日：2015-01-20

申请人： HeonJong Shin ,  SungMin Kim ,  ByungSeo Kim ,  Sunhom Steve Paak ,  Hyunjun Bae

发明人： HeonJong Shin ,  SungMin Kim ,  ByungSeo Kim ,  Sunhom Steve Paak ,  Hyunjun Bae

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L21/76202 ,  H01L21/265 ,  H01L21/324 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851

摘要： The inventive concepts provide semiconductor devices and methods of manufacturing the same. Semiconductor devices of the inventive concepts may include a fin region comprising a first fin subregion and a second fin subregion separated and isolated from each other by an isolation insulating layer disposed therebetween, a first gate intersecting the first fin subregion, a second gate intersecting the second fin subregion, and a third gate intersecting the isolation insulating layer.

摘要翻译： 本发明构思提供半导体器件及其制造方法。 本发明构思的半导体器件可以包括散热片区域，其包括通过设置在其间的隔离绝缘层彼此分离和隔离的第一鳍片区域和第二鳍片区域，与第一鳍片区域交叉的第一栅极，与第二鳍片相交的第二栅极 翅片子区域和与隔离绝缘层相交的第三栅极。

公开(公告)号：US09515172B2

公开(公告)日：2016-12-06

申请号：US14600689

申请日：2015-01-20

申请人： HeonJong Shin ,  SungMin Kim ,  ByungSeo Kim ,  Sunhom Steve Paak ,  Hyunjun Bae

发明人： HeonJong Shin ,  SungMin Kim ,  ByungSeo Kim ,  Sunhom Steve Paak ,  Hyunjun Bae

IPC分类号： H01L29/84 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088

CPC分类号： H01L21/76202 ,  H01L21/265 ,  H01L21/324 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851

摘要： The inventive concepts provide semiconductor devices and methods of manufacturing the same. Semiconductor devices of the inventive concepts may include a fin region comprising a first fin subregion and a second fin subregion separated and isolated from each other by an isolation insulating layer disposed therebetween, a first gate intersecting the first fin subregion, a second gate intersecting the second fin subregion, and a third gate intersecting the isolation insulating layer.

摘要翻译： 本发明构思提供半导体器件及其制造方法。 本发明构思的半导体器件可以包括散热片区域，其包括通过设置在其间的隔离绝缘层彼此分离和隔离的第一鳍片区域和第二鳍片区域，与第一鳍片区域交叉的第一栅极，与第二鳍片相交的第二栅极 翅片子区域和与隔离绝缘层相交的第三栅极。