公开(公告)号：US07550327B2

公开(公告)日：2009-06-23

申请号：US11607845

申请日：2006-12-04

申请人： Chang Deok Lee ,  Hyun Seok Hong

发明人： Chang Deok Lee ,  Hyun Seok Hong

IPC分类号： H01L21/00

CPC分类号： H01L27/1288 ,  G02F1/13458 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L27/1214

摘要： This invention provides method for fabricating a thin film transistor substrate that is adaptive for forming a good pattern design and also removing a stepped difference using a three-mask process.

摘要翻译： 本发明提供了一种用于制造薄膜晶体管基板的方法，该薄膜晶体管基板适于形成良好的图案设计，并且还使用三屏蔽工艺去除阶梯差。

公开(公告)号：US20070155068A1

公开(公告)日：2007-07-05

申请号：US11607845

申请日：2006-12-04

申请人： Chang Deok Lee ,  Hyun Seok Hong

发明人： Chang Deok Lee ,  Hyun Seok Hong

IPC分类号： H01L21/84

CPC分类号： H01L27/1288 ,  G02F1/13458 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L27/1214

摘要： This invention provides method for fabricating a thin film transistor substrate that is adaptive for forming a good pattern design and also removing a stepped difference using a three-mask process.

摘要翻译： 本发明提供了一种用于制造薄膜晶体管基板的方法，该薄膜晶体管基板适于形成良好的图案设计，并且还使用三屏蔽工艺去除阶梯差。

公开(公告)号：US08582075B2

公开(公告)日：2013-11-12

申请号：US11646240

申请日：2006-12-28

申请人： Hyun Seok Hong

发明人： Hyun Seok Hong

IPC分类号： G02F1/1339

CPC分类号： G02F1/1339 ,  G02F1/133351

摘要： A method for fabricating a liquid crystal display (LCD) device includes preparing a lower substrate and an upper substrate; forming a plurality of seal patterns on any one of the upper and lower substrates, each seal pattern including a main pattern and an injection port pattern, wherein a width of the injection port pattern is smaller than a width of the main pattern; bonding the upper and lower substrates to each other using the plurality of seal patterns; and cutting the bonded upper and lower substrates into a plurality of unit cells.

摘要翻译： 一种制造液晶显示（LCD）装置的方法，包括制备下基板和上基板; 在所述上基板和所述下基板中的任一个上形成多个密封图案，每个密封图案包括主图案和注入端口图案，其中所述注入端口图案的宽度小于所述主图案的宽度; 使用所述多个密封图案将所述上下基板彼此接合; 以及将粘合的上基板和下基板切割成多个单元电池。

公开(公告)号：US08110830B2

公开(公告)日：2012-02-07

申请号：US12003626

申请日：2007-12-28

申请人： Joo Soo Lim ,  Hyun Seok Hong ,  Chang Bin Lee

发明人： Joo Soo Lim ,  Hyun Seok Hong ,  Chang Bin Lee

IPC分类号： H01L21/00 ,  H01L33/00

CPC分类号： H01L27/1288 ,  G02F1/136227 ,  G02F2001/136231 ,  G02F2001/136236 ,  H01L27/1214 ,  H01L2924/0002 ,  H01L2924/00

摘要： A thin film transistor (TFT) array substrate and a method of manufacturing the same that is capable of decreasing the number of usage of exposure masks to reduce the process time and the process costs and excessively etching a passivation film below a photoresist pattern to easily perform a lift-off process of the photoresist pattern are disclosed. The TFT array substrate includes a gate line layer including a gate line formed on a substrate, a gate electrode diverging from the gate line, and a gate pad formed at the end of the gate line, a gate insulation film formed on the gate line layer, a semiconductor layer formed on the gate insulation film above the gate electrode, a data line layer including a data line intersecting the gate line, source and drain electrodes formed at opposite sides of the semiconductor layer, and a data pad formed at the end of the data line, a pixel electrode contacting the drain electrode, first and second oxidation preventing films contacting the gate pad and the data pad, and an at least two-layered passivation film deposited on the data line layer. The uppermost layer of the at least two-layered passivation film is formed at the remaining region excluding a region where the pixel electrode and the first and second oxidation preventing films are formed.

摘要翻译： 一种薄膜晶体管（TFT）阵列基板及其制造方法，其能够减少曝光掩模的使用次数以减少处理时间和处理成本，并且过度地蚀刻光致抗蚀剂图案之下的钝化膜以容易地执行 公开了光致抗蚀剂图案的剥离过程。 TFT阵列基板包括栅极线层，栅极线包括形成在基板上的栅极线，从栅极线发散的栅电极和形成在栅极线的端部的栅极焊盘，形成在栅极线层上的栅极绝缘膜 形成在栅极电极上方的栅极绝缘膜上的半导体层，包括与栅极线交叉的数据线的数据线层，形成在半导体层的相对侧的源极和漏极;以及形成在栅极绝缘膜的末端的数据焊盘 数据线，与漏电极接触的像素电极，与栅极焊盘和数据焊盘接触的第一和第二氧化防止膜以及沉积在数据线层上的至少两层钝化膜。 至少两层钝化膜的最上层形成在除了形成像素电极和第一和第二氧化防止膜的区域之外的剩余区域。

公开(公告)号：US20080169470A1

公开(公告)日：2008-07-17

申请号：US12003626

申请日：2007-12-28

申请人： Joo Soo Lim ,  Hyun Seok Hong ,  Chang Bin Lee

发明人： Joo Soo Lim ,  Hyun Seok Hong ,  Chang Bin Lee

IPC分类号： H01L33/00 ,  H01L21/00

CPC分类号： H01L27/1288 ,  G02F1/136227 ,  G02F2001/136231 ,  G02F2001/136236 ,  H01L27/1214 ,  H01L2924/0002 ,  H01L2924/00

摘要： A thin film transistor (TFT) array substrate and a method of manufacturing the same that is capable of decreasing the number of usage of exposure masks to reduce the process time and the process costs and excessively etching a passivation film below a photoresist pattern to easily perform a lift-off process of the photoresist pattern are disclosed. The TFT array substrate includes a gate line layer including a gate line formed on a substrate, a gate electrode diverging from the gate line, and a gate pad formed at the end of the gate line, a gate insulation film formed on the gate line layer, a semiconductor layer formed on the gate insulation film above the gate electrode, a data line layer including a data line intersecting the gate line, source and drain electrodes formed at opposite sides of the semiconductor layer, and a data pad formed at the end of the data line, a pixel electrode contacting the drain electrode, first and second oxidation preventing films contacting the gate pad and the data pad, and an at least two-layered passivation film deposited on the data line layer. The uppermost layer of the at least two-layered passivation film is formed at the remaining region excluding a region where the pixel electrode and the first and second oxidation preventing films are formed.

摘要翻译： 一种薄膜晶体管（TFT）阵列基板及其制造方法，其能够减少曝光掩模的使用次数以减少处理时间和处理成本，并且过度地蚀刻光致抗蚀剂图案之下的钝化膜以容易地执行 公开了光致抗蚀剂图案的剥离过程。 TFT阵列基板包括栅极线层，栅极线包括形成在基板上的栅极线，从栅极线发散的栅电极和形成在栅极线的端部的栅极焊盘，形成在栅极线层上的栅极绝缘膜 形成在栅极电极上方的栅极绝缘膜上的半导体层，包括与栅极线交叉的数据线的数据线层，形成在半导体层的相对侧的源极和漏极;以及形成在栅极绝缘膜的末端的数据焊盘 数据线，与漏电极接触的像素电极，与栅极焊盘和数据焊盘接触的第一和第二氧化防止膜以及沉积在数据线层上的至少两层钝化膜。 至少两层钝化膜的最上层形成在除了形成像素电极和第一和第二氧化防止膜的区域之外的剩余区域。