公开(公告)号：US08446017B2

公开(公告)日：2013-05-21

申请号：US12562387

申请日：2009-09-18

申请人： Jong Sik Paek ,  In Bae Park ,  Chang Deok Lee

发明人： Jong Sik Paek ,  In Bae Park ,  Chang Deok Lee

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L25/0657 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/481 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/221 ,  H01L2224/24051 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/81815 ,  H01L2224/82106 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2224/83

摘要： A stackable wafer level package and a fabricating method thereof are disclosed. In the stackable wafer level package, bond pads (or redistribution layers) are arranged on a bottom semiconductor die, and metal pillars are formed on some of the bond pads positioned around the edges of the bottom semiconductor die. A top semiconductor die is electrically connected to the other bond pads, on which the metal pillars are not formed, positioned around the center of the bottom semiconductor die through conductive bumps. The metal pillars and the top semiconductor die are encapsulated by an encapsulant. A plurality of interconnection patterns electrically connected to the metal pillars are formed on the surface of the encapsulant. Solder balls are attached to the interconnection patterns. Due to this stack structure, the wafer level package is reduced in thickness and footprint. Therefore, the wafer level package is highly suitable for mobile applications.

摘要翻译： 公开了一种可堆叠的晶片级封装及其制造方法。 在可堆叠晶片级封装中，接合焊盘（或再分配层）被布置在底部半导体管芯上，并且金属柱形成在位于底部半导体管芯的边缘周围的一些接合焊盘上。 顶部半导体管芯电连接到其上未形成金属柱的其它接合焊盘，通过导电凸块定位在底部半导体管芯的中心附近。 金属柱和顶部半导体管芯由密封剂封装。 电连接到金属柱的多个互连图案形成在密封剂的表面上。 焊球附接到互连图案。 由于这种堆叠结构，晶片级封装的厚度和占地面积减小。 因此，晶片级封装非常适合于移动应用。

公开(公告)号：US20110068427A1

公开(公告)日：2011-03-24

申请号：US12562387

申请日：2009-09-18

申请人： Jong Sik PAEK ,  In Bae PARK ,  Chang Deok LEE

发明人： Jong Sik PAEK ,  In Bae PARK ,  Chang Deok LEE

IPC分类号： H01L31/0203 ,  H01L23/498 ,  H01L21/98

CPC分类号： H01L25/0657 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/481 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/221 ,  H01L2224/24051 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/81815 ,  H01L2224/82106 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2224/83

摘要： A stackable wafer level package and a fabricating method thereof are disclosed. In the stackable wafer level package, bond pads (or redistribution layers) are arranged on a bottom semiconductor die, and metal pillars are formed on some of the bond pads positioned around the edges of the bottom semiconductor die. A top semiconductor die is electrically connected to the other bond pads, on which the metal pillars are not formed, positioned around the center of the bottom semiconductor die through conductive bumps. The metal pillars and the top semiconductor die are encapsulated by an encapsulant. A plurality of interconnection patterns electrically connected to the metal pillars are formed on the surface of the encapsulant. Solder balls are attached to the interconnection patterns. Due to this stack structure, the wafer level package is reduced in thickness and footprint. Therefore, the wafer level package is highly suitable for mobile applications.

摘要翻译： 公开了一种可堆叠的晶片级封装及其制造方法。 在可堆叠晶片级封装中，接合焊盘（或再分配层）被布置在底部半导体管芯上，并且金属柱形成在位于底部半导体管芯的边缘周围的一些接合焊盘上。 顶部半导体管芯电连接到其上未形成金属柱的其它接合焊盘，通过导电凸块定位在底部半导体管芯的中心附近。 金属柱和顶部半导体管芯由密封剂封装。 电连接到金属柱的多个互连图案形成在密封剂的表面上。 焊球附接到互连图案。 由于这种堆叠结构，晶片级封装的厚度和占地面积减小。 因此，晶片级封装非常适合于移动应用。

公开(公告)号：US07705954B2

公开(公告)日：2010-04-27

申请号：US11448261

申请日：2006-06-07

申请人： Chang Deok Lee

发明人： Chang Deok Lee

IPC分类号： G02F1/1333 ,  G02F1/1345

CPC分类号： G02F1/136286 ,  G02F1/13458 ,  G02F2001/13629 ,  G02F2001/136295

摘要： An LCD and a fabrication method thereof are provided. The LCD includes a gate pad. The gate pad includes a gate ITO electrode formed on a substrate, a first and a second gate pad bottom electrode formed on a predetermined region of the gate ITO electrode, a gate insulating layer formed on the first and the second gate pad bottom electrode, a passivation layer formed on the gate insulating layer, a gate pad top electrode formed on the passivation layer, and at least one contact hole. The LCD further comprises a liquid crystal panel having a gate line that has a dual structure integrally formed with the first gate pad bottom electrode and the second gate pad bottom electrode.

摘要翻译： 提供了一种LCD及其制造方法。 LCD包括一个门板。 栅极焊盘包括形成在基板上的栅极ITO电极，形成在栅极ITO电极的预定区域上的第一和第二栅极焊盘底部电极，形成在第一和第二栅极焊盘底部电极上的栅极绝缘层， 形成在栅极绝缘层上的钝化层，形成在钝化层上的栅极焊盘顶部电极以及至少一个接触孔。 LCD还包括具有栅极线的液晶面板，栅极线具有与第一栅极焊盘底部电极和第二栅极焊盘底部电极一体形成的双重结构。

公开(公告)号：US08148724B2

公开(公告)日：2012-04-03

申请号：US12472098

申请日：2009-05-26

申请人： Chang-Deok Lee ,  Hyung-Beom Shin ,  Seok Kim

发明人： Chang-Deok Lee ,  Hyung-Beom Shin ,  Seok Kim

IPC分类号： H01L29/04 ,  H01L29/10 ,  H01L21/84

CPC分类号： G02F1/13458 ,  H01L27/124

摘要： A liquid crystal display device includes a gate line and a data line on a substrate crossing each other to define a pixel region; a thin film transistor in the pixel region and connected to the gate line and the data line; a pixel electrode in the pixel region and connected to the thin film transistor; and a gate pad at an end of the gate line and a data pad at an end of the data line, at least one of the gate pad and the data pad including: a pad electrode including at least one pad contact hole therein along with a passivation layer, the passivation layer on the pad electrode, at least one side of the pad contact hole having an uneven shape in plane; and a pad electrode terminal contacting inner side surfaces of the pad electrode surrounding the pad contact hole.

摘要翻译： 液晶显示装置包括在彼此交叉以限定像素区域的基板上的栅极线和数据线; 像素区域中的薄膜晶体管，并连接到栅极线和数据线; 像素电极，并连接到薄膜晶体管; 以及位于栅极线的端部的栅极焊盘和在数据线的末端的数据焊盘，栅极焊盘和数据焊盘中的至少一个包括：焊盘电极，其中包括至少一个焊盘接触孔以及 钝化层，焊盘电极上的钝化层，焊盘接触孔的至少一侧在平面内具有不均匀的形状; 以及焊盘电极端子，其接触围绕焊盘接触孔的焊盘电极的内侧表面。

公开(公告)号：US08125064B1

公开(公告)日：2012-02-28

申请号：US12181256

申请日：2008-07-28

申请人： Chang Deok Lee ,  Do Hyun Na

发明人： Chang Deok Lee ,  Do Hyun Na

IPC分类号： H01L23/06

CPC分类号： H01L23/49838 ,  H01L23/13 ,  H01L23/142 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15151 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In accordance with the present invention, there is provided a semiconductor package and a fabrication method thereof. The semiconductor package is provided with a substrate made of metal, thereby improving efficiency of thermal emission from a semiconductor die mounted to the substrate, and simplifying the fabrication process for the substrate which reduces fabricating costs. Further, unlike a conventional land, a rivet electrically insulated with the substrate is inserted into a corresponding hole of the substrate, the upper and lower surfaces of the rivet being removed to form land, thereby simplifying the fabrication process for the substrate which further reduces fabricating costs.

摘要翻译： 根据本发明，提供一种半导体封装及其制造方法。 半导体封装设置有由金属制成的基板，从而提高了从安装到基板的半导体管芯的热发射效率，并且简化了基板的制造工艺，从而降低了制造成本。 此外，与传统的焊盘不同，将与基板电绝缘的铆钉插入到基板的相应的孔中，去除铆钉的上表面和下表面以形成焊盘，从而简化了基板的制造工艺，进一步减少了制造 费用

公开(公告)号：US07808084B1

公开(公告)日：2010-10-05

申请号：US12116127

申请日：2008-05-06

申请人： Chang Deok Lee ,  Do Hyun Na

发明人： Chang Deok Lee ,  Do Hyun Na

IPC分类号： H01L23/495

CPC分类号： H01L23/49541 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49551 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/10162 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Disclosed is a lead frame, a semiconductor device and a fabrication method related to the semiconductor device. Since the lead frame has a land connecting bar, an upper surface of which is half-etched, the land connecting bar is more easily removed by a blade than a conventional land connecting bar in a fabrication process for the semiconductor device. Accordingly, stress applied to the lands when the land connecting bar is removed is reduced, and a flatness of the lands is maintained. Also, first and second lands constituting the lands are alternately formed with the land connecting bar, leads are alternately formed with the second lands, and wire bonding regions of the leads are positioned on a plane higher than the second lands. Accordingly, an interval between the conductive wires can be constantly maintained and the conductive wires have different traces, thus preventing a short between the conductive wires due to wire sweeping in an encapsulation process.

摘要翻译： 公开了与半导体器件相关的引线框架，半导体器件和制造方法。 由于引线框架具有上表面被半蚀刻的焊盘连接杆，所以在半导体器件的制造工艺中，焊盘连接杆比通常的焊盘连接杆更容易被刀片除去。 因此，减少了当连接杆被移除时施加到焊盘上的应力，并且保持焊盘的平坦度。 此外，构成焊盘的第一和第二焊盘与焊盘连接杆交替地形成，引线与第二焊盘交替地形成，并且引线的引线接合区域位于比第二焊盘高的平面上。 因此，可以恒定地保持导线之间的间隔，并且导线具有不同的迹线，从而防止由于封装处理中的线扫描导致的导线之间的短路。

公开(公告)号：US07760317B2

公开(公告)日：2010-07-20

申请号：US10962452

申请日：2004-10-13

申请人： Byoung Ho Lim ,  Soon Sung Yoo ,  Chang Deok Lee ,  Seung Hee Nam ,  Jae Young Oh ,  Hong Sik Kim ,  Hee Young Kwack

发明人： Byoung Ho Lim ,  Soon Sung Yoo ,  Chang Deok Lee ,  Seung Hee Nam ,  Jae Young Oh ,  Hong Sik Kim ,  Hee Young Kwack

IPC分类号： G02F1/1345 ,  G09G3/36

CPC分类号： G02F1/136286 ,  G02F1/136227 ,  G02F2001/136231 ,  G02F2001/136254

摘要： A TFT array substrate is fabricated in a reduced number of processes. The TFT array substrate includes gate and data pads with enlarged contact areas to facilitate contact with an inspecting pin of an inspection device. An LCD incorporating the TFT array substrate is inspected by contacting the inspecting pin to the gate and data pads. The TFT array substrate includes first, second, and third conductive pattern groups. The first conductive pattern group includes a gate electrode, a gate line, and a lower gate pad electrode. The second conductive pattern group includes source and drain electrodes, a data line, and a lower data pad electrode. The third conductive pattern group includes a pixel electrode, and upper gate and data pad electrodes. A semiconductor pattern is along and beneath the second conductive pattern group. Gate insulating and protective film patterns are at areas not occupied by the third conductive pattern group.

摘要翻译： 以减少数量的工艺制造TFT阵列基板。 TFT阵列基板包括具有扩大的接触面积的栅极和数据焊盘，以便于与检查装置的检查销接触。 通过将检查引脚接触到栅极和数据焊盘来检查结合了TFT阵列基板的LCD。 TFT阵列基板包括第一，第二和第三导电图案组。 第一导电图案组包括栅电极，栅极线和下栅极焊盘电极。 第二导电图案组包括源极和漏极，数据线和下部数据焊盘电极。 第三导电图案组包括像素电极和上栅极和数据焊盘电极。 半导体图案沿着第二导电图案组的下方。 栅极绝缘和保护膜图案在未被第三导电图案组占据的区域。

公开(公告)号：US20070155068A1

公开(公告)日：2007-07-05

申请号：US11607845

申请日：2006-12-04

申请人： Chang Deok Lee ,  Hyun Seok Hong

发明人： Chang Deok Lee ,  Hyun Seok Hong

IPC分类号： H01L21/84

CPC分类号： H01L27/1288 ,  G02F1/13458 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L27/1214

摘要： This invention provides method for fabricating a thin film transistor substrate that is adaptive for forming a good pattern design and also removing a stepped difference using a three-mask process.

摘要翻译： 本发明提供了一种用于制造薄膜晶体管基板的方法，该薄膜晶体管基板适于形成良好的图案设计，并且还使用三屏蔽工艺去除阶梯差。

公开(公告)号：US20100127263A1

公开(公告)日：2010-05-27

申请号：US12472098

申请日：2009-05-26

申请人： Chang-Deok Lee ,  Hyung-Beom Shin ,  Seok Kim

发明人： Chang-Deok Lee ,  Hyung-Beom Shin ,  Seok Kim

IPC分类号： H01L33/00 ,  H01L21/336

CPC分类号： G02F1/13458 ,  H01L27/124

摘要： A liquid crystal display device includes a gate line and a data line on a substrate crossing each other to define a pixel region; a thin film transistor in the pixel region and connected to the gate line and the data line; a pixel electrode in the pixel region and connected to the thin film transistor; and a gate pad at an end of the gate line and a data pad at an end of the data line, at least one of the gate pad and the data pad including: a pad electrode including at least one pad contact hole therein along with a passivation layer, the passivation layer on the pad electrode, at least one side of the pad contact hole having an uneven shape in plane; and a pad electrode terminal contacting inner side surfaces of the pad electrode surrounding the pad contact hole.

摘要翻译： 液晶显示装置包括在彼此交叉以限定像素区域的基板上的栅极线和数据线; 像素区域中的薄膜晶体管，并连接到栅极线和数据线; 像素电极，并连接到薄膜晶体管; 以及位于栅极线的端部的栅极焊盘和在数据线的末端的数据焊盘，栅极焊盘和数据焊盘中的至少一个包括：焊盘电极，其中包括至少一个焊盘接触孔以及 钝化层，焊盘电极上的钝化层，焊盘接触孔的至少一侧在平面内具有不均匀的形状; 以及焊盘电极端子，其接触围绕焊盘接触孔的焊盘电极的内侧表面。

公开(公告)号：US07359204B1

公开(公告)日：2008-04-15

申请号：US11355092

申请日：2006-02-15

申请人： Sang Jae Jang ,  Chul Woo Park ,  Jong Woon Choi ,  Jae Dong Kim ,  Choon Heung Lee ,  Chang Deok Lee

发明人： Sang Jae Jang ,  Chul Woo Park ,  Jong Woon Choi ,  Jae Dong Kim ,  Choon Heung Lee ,  Chang Deok Lee

IPC分类号： H05K7/20

CPC分类号： H05K5/0256 ,  G06K19/07 ,  G06K19/07732

摘要： A memory card including a module comprising at least a printed circuit board having an electronic circuit device mounted thereto and at least one I/O pad and at least one test pad disposed thereon. The module is inserted into a complementary cavity formed within a case of the memory card, such case generally defining the outer appearance of the memory card. The module is secured within the cavity of the case through the use of an adhesive. In each embodiment of the present invention, first and second covers are movably attached to a case for selectively covering or exposing the I/O pads and the test features/pads of the module of the memory card.

摘要翻译： 一种存储卡，包括至少包括安装有电子电路装置的印刷电路板和至少一个I / O焊盘和至少一个设置在其上的测试焊盘的模块。 模块被插入形成在存储卡的壳体内的互补空腔中，这种情况通常限定存储卡的外观。 模块通过使用粘合剂固定在外壳的腔内。 在本发明的每个实施例中，第一和第二盖可移动地附接到壳体，用于选择性地覆盖或暴露存储卡模块的I / O焊盘和测试特征/焊盘。