公开(公告)号：US20070130568A1

公开(公告)日：2007-06-07

申请号：US11453288

申请日：2006-06-15

申请人： Chang Jung ,  Dae Lim ,  Jae Lee ,  Sang Han

发明人： Chang Jung ,  Dae Lim ,  Jae Lee ,  Sang Han

IPC分类号： G06F9/46

CPC分类号： G06F8/456 ,  G06F9/5066 ,  G06F11/3404 ,  G06F2201/88

摘要： Provided is a parallel program execution method in which in order to reflect structural characteristics of a multithreaded processor-based parallel system, performance of the parallel loop is predicted while compiling or executing using a performance prediction model and then the parallel program is executed using an adaptive execution method. The method includes the steps of: generating as many threads as the number of physical processors of the parallel system in order to execute at least one parallel loop contained in the parallel program; by the generated threads, executing at least one single loop of each parallel loop; measuring an execution time, the number of executed instructions, and the number of cache misses for each parallel loop; determining an execution mode of each parallel loop by determining the number of threads used to execute each parallel loop based on the measured values; and allocating the threads to each physical processor according to the result of the determination to execute each parallel loop. The method significantly improves the performance of the parallel program driven in the multithreaded processor-based parallel system.

摘要翻译： 提供了一种并行程序执行方法，其中为了反映基于多线程处理器的并行系统的结构特征，在使用性能预测模型编译或执行时预测并行循环的性能，然后使用自适应 执行方式。 该方法包括以下步骤：生成与并行系统的物理处理器的数量一样多的线程，以便执行并行程序中包含的至少一个并行循环; 通过生成的线程执行每个并行循环的至少一个单个循环; 测量执行时间，执行指令的数量以及每个并行循环的高速缓存未命中数; 通过基于测量值确定用于执行每个并行循环的线程数，确定每个并行循环的执行模式; 以及根据确定的结果将线程分配给每个物理处理器以执行每个并行循环。 该方法显着提高了在基于多线程处理器的并行系统中驱动的并行程序的性能。

公开(公告)号：US08208316B2

公开(公告)日：2012-06-26

申请号：US12194142

申请日：2008-08-19

申请人： Nan Chen ,  Chang Jung ,  Zhiqin Chen

发明人： Nan Chen ,  Chang Jung ,  Zhiqin Chen

IPC分类号： G11C7/06

CPC分类号： G11C7/12 ,  G11C11/409 ,  G11C2207/005

摘要： A sense margin is improved for a read path in a memory array. Embodiments improve the sense margin by using gates with a lower threshold voltage in a read column multiplexer. A cross coupled keeper can further improve the sense margin by increasing a voltage level on a bit line storing a high value, thereby counteracting leakage on the “high” bit line.

摘要翻译： 针对存储器阵列中的读取路径改进了检测边缘。 实施例通过在读列多路复用器中使用具有较低阈值电压的门来提高感测余量。 交叉耦合保持器可以通过增加存储高值的位线上的电压电平来进一步提高感测容限，从而抵消“高”位线上的泄漏。

公开(公告)号：US20060089875A1

公开(公告)日：2006-04-27

申请号：US10970934

申请日：2004-10-22

申请人： Dae Park ,  Chang Jung ,  Bo Lee ,  Brian Chung

发明人： Dae Park ,  Chang Jung ,  Bo Lee ,  Brian Chung

IPC分类号： G06Q30/00

CPC分类号： G06Q30/02 ,  G06Q30/0222 ,  G06Q30/0226

摘要： An integrated online purchase reward system includes one or more first information processing devices, one or more second information processing devices, a network, and one or more purchase transaction monitoring devices which read in a purchase transaction medium, and print out purchase transaction records on the purchase transaction media as a hard copy. The first information processing devices receive, process, and distribute data, and respond to requests from the second information processing devices. The first information processing device includes database, and the second information processing devices are connected with the purchase transaction monitoring device. The network works on a TCP/IP Protocol environment and connects the first and the second information processing devices. The purchase transaction information including reward or gift is printed on a PET card through line thermal printing. A person with an appropriate authorization can access the first information processing device through internet and retrieve data.

摘要翻译： 集成的在线购买奖励系统包括一个或多个第一信息处理设备，一个或多个第二信息处理设备，网络和在购买交易介质中读取的一个或多个购买交易监控设备，并且在 购买交易媒体作为硬拷贝。 第一信息处理设备接收，处理和分发数据，并响应来自第二信息处理设备的请求。 第一信息处理装置包括数据库，第二信息处理装置与购买交易监视装置连接。 该网络工作于TCP / IP协议环境，并连接第一和第二信息处理设备。 包括奖励或礼品在内的购买交易信息通过热敏打印印在PET卡上。 具有适当授权的人可以通过互联网访问第一信息处理设备并检索数据。

公开(公告)号：US20060080861A1

公开(公告)日：2006-04-20

申请号：US11241971

申请日：2005-10-04

申请人： Wan Park ,  Chang Jung

发明人： Wan Park ,  Chang Jung

IPC分类号： A43B15/00 ,  A43C15/00

CPC分类号： A43B13/26 ,  A43B3/16 ,  A43B5/185 ,  A43C15/005 ,  A43C15/02 ,  A43C15/06

摘要： Disclosed is a safety crampon with generality put on, which encircles front/rear/left/right sides of shoes around a spike pad to elastically press and grip them so that the crampon is not come off from the shoes, thereby ensuring safety. Also, the safety crampon has excellent wearing feeling and walking owing to characteristics of an elastic material, can be put on all kinds of shoes including mountain-climbing boots, high-heeled shoes, and rubber shoes, allows a user to safely climb a mountain and safely walk on a skiddy icy road of the ground, and has a conveniently portable advantage. The antiskid safety crampon includes a spike pad made of an elastic material such as a foaming resin or rubber and provided with a plurality of spikes, a hook formed in the spike pad in a single body with the spike pad to be fixably hooked over shoes, a limb band oriented from four edges of the spike pad toward the contour, and a ring band inscribed in a front end of the limb band, wherein the spike pad, the hook, the limb band and the ring band are formed of an elastic material in a single body with one another.

摘要翻译： 公开了一种通用的安全钳，其围绕钉垫周围的鞋子的前/后/左/右侧弹性地按压并夹紧，使得冰爪不会从鞋上脱落，从而确保安全。 此外，由于弹性材料的特点，安全钳具有优异的穿着感和行走能力，可以放在各种鞋子上，包括登山靴，高跟鞋和橡胶鞋，允许用户安全地爬山 并安全地走在地面上冰冷的冰冷的道路上，具有方便便携的优点。 防滑安全系统包括由诸如发泡树脂或橡胶的弹性材料制成的钉垫，并且设置有多个钉，钩形成在单个主体中的钉垫中，钉垫可固定地钩在鞋上， 从所述尖钉垫的四个边缘朝向轮廓定向的肢体带，以及内嵌在所述肢体带的前端中的环带，其中所述钉垫，钩，所述肢带和所述环带由弹性材料形成 在一个单一的身体彼此。

公开(公告)号：US20070082499A1

公开(公告)日：2007-04-12

申请号：US11489465

申请日：2006-07-20

申请人： Chang Jung ,  Tae Kim ,  Jin Lee ,  June Koo

发明人： Chang Jung ,  Tae Kim ,  Jin Lee ,  June Koo

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/6715 ,  G03F7/162

摘要： A photoresist coating apparatus, medium, and method for efficiently spraying a liquid photoresist to maintain an atmosphere of ionized solvent vapor between a substrate and a spray nozzle of an upper portion by using a vapor inducing pipe supplying ionized solvent vapor, with the atmosphere being maintained by differently biasing a lower portion supporting the substrate and a plate of the upper portion. Photoresist can be evenly coated over the entire surface of the substrate while reducing the loss of sprayed photoresist droplets.

摘要翻译： 一种光致抗蚀剂涂覆装置，介质和方法，用于通过使用供应离子化溶剂蒸气的蒸气诱导管，保持气氛来有效地喷射液体光致抗蚀剂以保持基板和上部喷嘴之间的离子化溶剂蒸气的气氛 通过不同地偏置支撑衬底的下部和上部的板。 光致抗蚀剂可以均匀地涂覆在基材的整个表面上，同时减少喷涂的光致抗蚀剂液滴的损失。

公开(公告)号：US20070077352A1

公开(公告)日：2007-04-05

申请号：US11511435

申请日：2006-08-29

申请人： June Koo ,  Tae Kim ,  Jin Lee ,  Chang Jung

发明人： June Koo ,  Tae Kim ,  Jin Lee ,  Chang Jung

IPC分类号： B05D3/12 ,  B05D7/00 ,  B05C11/02 ,  B05B7/06

CPC分类号： G03F7/162 ,  G03F7/168

摘要： A photoresist coating system and method solving an edge bead problem that occurs in photoresist coating by adding at least one of high boiling point solvent, which may generate a film on the surface of a solvent having a higher boiling point than a solvent contained in a liquid photoresist or the surface of the liquid photoresist, or by supplying a surfactant to an edge of the wafer, with the surfactant being combinable with the solvent or capable of forming a film on the solvent.

摘要翻译： 一种光致抗蚀剂涂覆系统和方法，其通过加入至少一种高沸点溶剂来解决在光致抗蚀剂涂层中发生的边缘珠粒问题，所述高沸点溶剂可在具有高于沸点的溶剂的表面上产生比液体中所含的溶剂产生的膜 光致抗蚀剂或液态光致抗蚀剂的表面，或者通过向晶片的边缘供给表面活性剂，表面活性剂可与溶剂组合或能够在溶剂上形成膜。

公开(公告)号：US20070004458A1

公开(公告)日：2007-01-04

申请号：US10560149

申请日：2004-07-23

申请人： Chang Jung

发明人： Chang Jung

IPC分类号： H04B1/38

CPC分类号： H04B1/406

摘要： The present invention relates to a method of designing a micro-Base Transceiver System (BTS) of a CDMA system. In a conventional micro-BTS, one Intermediate Frequency (IF) board has only one sector or Frequency Assignment (FA) therein, and a digital combiner and a switching logic are comprised in individual channel cards and IF boards. Thus, the FA to an IF board cannot avoid being fixed. However, according to the present invention, a digital combiner and a switching logic are transplanted in a main board of a micro-BTS, which operates as a backplane. By using this construction, the present invention can achieve a more efficient interface between a channel card and an IF board, and further increase the flexibility in establishing FAs.

摘要翻译： 本发明涉及CDMA系统的微型基站收发系统（BTS）的设计方法。 在传统的微型BTS中，一个中频（IF）板在其中仅具有一个扇区或频率分配（FA），并且数字组合器和开关逻辑包括在各个通道卡和IF板中。 因此，中信证券董事会的FA不能避免被修正。 然而，根据本发明，数字组合器和开关逻辑被移植到作为背板操作的微BTS的主板中。 通过使用这种结构，本发明可以实现通道卡和IF板之间的更有效的接口，并进一步提高建立FA的灵活性。

公开(公告)号：US07746722B2

公开(公告)日：2010-06-29

申请号：US12140502

申请日：2008-06-17

申请人： Jeffrey Scott Brown ,  Chang Jung

发明人： Jeffrey Scott Brown ,  Chang Jung

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C5/025 ,  G11C11/417

摘要： A self-timed memory array is disclosed, in which segmentability and metal-programmability are supported while minimizing layout space. Self-timing row decoder circuits are placed at the top and bottom of the array adjacent to respective I/O blocks. A self-timing signal is routed from the top (resp. bottom) of the array to a point halfway down (resp. up) the memory array and then back to a self-timing row decoder at the top (resp. bottom) of the array. The same approach may also be used to account for the bitline wire delay from the bottom (resp. top) of the array to the sense amplifiers in the I/O block. Further flexibility in wire routing is provided by eliminating metal routing layers from unneeded memory cells, and a programmable gate array may be used to allow an arbitrary word size to be chosen for the memory.

摘要翻译： 公开了一种自定时存储器阵列，其中支持可分割性和金属可编程性，同时最小化布局空间。 自定时行解码器电路放置在与相应I / O块相邻的阵列的顶部和底部。 自定时信号从阵列的顶部（相应的底部）路由到存储器阵列的中途（分别向上）一点，然后返回到顶部（相应的底部）的自定时行解码器 阵列。 也可以使用相同的方法来解释从阵列的底部（相对顶部）到I / O块中的读出放大器的位线延迟。 通过从不需要的存储器单元中消除金属布线层来提供电线布线的进一步的灵活性，并且可以使用可编程门阵列来允许为存储器选择任意的字大小。

公开(公告)号：US20080253206A1

公开(公告)日：2008-10-16

申请号：US12140502

申请日：2008-06-17

申请人： Jeffrey Scott Brown ,  Chang Jung

发明人： Jeffrey Scott Brown ,  Chang Jung

IPC分类号： G11C7/00 ,  G06F17/50

CPC分类号： G11C8/10 ,  G11C5/025 ,  G11C11/417

摘要： A self-timed memory array is disclosed, in which segmentability and metal-programmability are supported while minimizing layout space. Self-timing row decoder circuits are placed at the top and bottom of the array adjacent to respective I/O blocks. A self-timing signal is routed from the top (resp. bottom) of the array to a point halfway down (resp. up) the memory array and then back to a self-timing row decoder at the top (resp. bottom) of the array. The same approach may also be used to account for the bitline wire delay from the bottom (resp. top) of the array to the sense amplifiers in the I/O block. Further flexibility in wire routing is provided by eliminating metal routing layers from unneeded memory cells, and a programmable gate array may be used to allow an arbitrary word size to be chosen for the memory.

摘要翻译： 公开了一种自定时存储器阵列，其中支持可分割性和金属可编程性，同时最小化布局空间。 自定时行解码器电路放置在与相应I / O块相邻的阵列的顶部和底部。 自定时信号从阵列的顶部（相应的底部）路由到存储器阵列的中途（分别向上）一点，然后返回到顶部（相应的底部）的自定时行解码器 阵列。 也可以使用相同的方法来解释从阵列的底部（相对顶部）到I / O块中的读出放大器的位线延迟。 通过从不需要的存储器单元中消除金属布线层来提供电线布线的进一步的灵活性，并且可以使用可编程门阵列来允许为存储器选择任意的字大小。

公开(公告)号：US20070109884A1

公开(公告)日：2007-05-17

申请号：US11282345

申请日：2005-11-17

申请人： Chang Jung

发明人： Chang Jung

IPC分类号： G11C29/00

CPC分类号： G11C7/22 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/222 ,  G11C8/16 ,  G11C2207/108 ,  G11C2207/2281 ,  G11C2207/229

摘要： A pseudo-dual port memory has a first port, a second port, and an array of six-transistor memory cells. A first memory access is initiated upon a rising edge of a first clock signal received onto the first port. A second memory access is initiated in response to a rising edge of a second clock signal received onto the second port. If the rising edge of the second clock signal occurs within a first period of time, then the second memory access is initiated immediately following completion of the first memory access in pseudo-dual port fashion. If the rising edge of the second clock signal occurs later within a second period of time, then the second memory access is delayed until after a second rising edge of the first clock signal. The durations of the first and second memory accesses do not depend on the duty cycles of the clock signals.

摘要翻译： 伪双端口存储器具有第一端口，第二端口和六晶体管存储器单元的阵列。 在接收到第一端口上的第一时钟信号的上升沿开始第一存储器访问。 响应于接收到第二端口的第二时钟信号的上升沿来启动第二存储器访问。 如果第二时钟信号的上升沿在第一时间段内发生，则在伪双端口方式完成第一存储器访问之后立即启动第二存储器访问。 如果第二时钟信号的上升沿在第二时间段内稍后发生，则第二存储器访问被延迟直到第一时钟信号的第二上升沿。 第一和第二存储器访问的持续时间不依赖于时钟信号的占空比。