公开(公告)号：US07253655B2

公开(公告)日：2007-08-07

申请号：US11218988

申请日：2005-09-01

申请人： Chang Ki Kwon ,  Greg Blodgett

发明人： Chang Ki Kwon ,  Greg Blodgett

IPC分类号： H03K19/003

CPC分类号： H03L7/00 ,  H03K19/00346

摘要： Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which the data segment is transmitted in response to the plurality of data segments that the other drivers will transmit. The adjustment may compensate for simultaneous switching noise and cross-talk by, for example, delaying the transmission of a data segment or changing the slew rate of the signal carrying the data segment.

公开(公告)号：US20070046331A1

公开(公告)日：2007-03-01

申请号：US11218988

申请日：2005-09-01

申请人： Chang Ki Kwon ,  Greg Blodgett

发明人： Chang Ki Kwon ,  Greg Blodgett

IPC分类号： H03K19/094

CPC分类号： H03L7/00 ,  H03K19/00346

摘要： Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which the data segment is transmitted in response to the plurality of data segments that the other drivers will transmit. The adjustment may compensate for simultaneous switching noise and cross-talk by, for example, delaying the transmission of a data segment or changing the slew rate of the signal carrying the data segment.

摘要翻译： 用于控制驱动器以减少数据相关噪声的技术，例如同时切换效果和串扰效应。 多个驱动器可以各自接收要发送的数据段和其他驱动器将发送的多个数据段。 驱动器控制器可以响应于其他驱动器将要发送的多个数据段来调整发送数据段的时间。 调整可以通过例如延迟数据段的传输或改变携带数据段的信号的转换速率来补偿同时的开关噪声和串扰。

公开(公告)号：US07521967B2

公开(公告)日：2009-04-21

申请号：US11881262

申请日：2007-07-26

申请人： Chang Ki Kwon ,  Greg Blodgett

发明人： Chang Ki Kwon ,  Greg Blodgett

IPC分类号： H03K19/0175

CPC分类号： H03L7/00 ,  H03K19/00346

摘要： Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which the data segment is transmitted in response to the plurality of data segments that the other drivers will transmit. The adjustment may compensate for simultaneous switching noise and cross-talk by, for example, delaying the transmission of a data segment or changing the slew rate of the signal carrying the data segment.

摘要翻译： 用于控制驱动器以减少数据相关噪声的技术，例如同时切换效果和串扰效应。 多个驱动器可以各自接收要发送的数据段和其他驱动器将发送的多个数据段。 驱动器控制器可以响应于其他驱动器将要发送的多个数据段来调整发送数据段的时间。 调整可以通过例如延迟数据段的传输或改变携带数据段的信号的转换速率来补偿同时的开关噪声和串扰。

公开(公告)号：US07606102B2

公开(公告)日：2009-10-20

申请号：US11509310

申请日：2006-08-24

申请人： Greg Blodgett

发明人： Greg Blodgett

IPC分类号： G11C17/18

CPC分类号： G11C17/16 ,  G11C29/787 ,  G11C29/812

摘要： A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using one or more least significant bits (LSBs) in the memory address stored in the fuse bank, thereby avoiding the need for a separate enable fuse. A reduction in the number of fuses results in space savings on the memory chip real estate and also savings in power consumption because of fewer fuses to be blown and read. With reduced fuse count, the yield of the memory chip's die may also be improved because of less number of defective fuses or failed fuse blows. The use of effective default state inversion for address fuses may further reduce the average number of fuses that need to be blown to repair a given non-redundant memory address. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

摘要翻译： 公开了一种存储器芯片设计方法，其中可以在不使能熔丝的情况下实现存储器芯片上的熔丝组。 可以通过使用存储在熔丝组中的存储器地址中的一个或多个最低有效位（LSB）来使能熔丝组，从而避免需要单独的使能熔丝。 保险丝数量的减少导致存储器芯片空间节省空间，并且由于更少的熔丝被熔化和读取而节省了功率消耗。 由于熔断器计数减少，存储器芯片的裸片的产量也可能由于缺少熔丝数量不足或保险丝熔断失败而得到改善。 对地址熔丝使用有效的默认状态反转可以进一步减少需要熔断的熔断器的平均数，以修复给定的非冗余存储器地址。 由于管理摘要的规则，本摘要不应用于解释索赔。

公开(公告)号：US20060181947A1

公开(公告)日：2006-08-17

申请号：US11402479

申请日：2006-04-11

申请人： Donald Morgan ,  Greg Blodgett

发明人： Donald Morgan ,  Greg Blodgett

IPC分类号： G11C7/00

CPC分类号： G11C11/40622 ,  G11C5/14 ,  G11C11/406 ,  G11C11/408 ,  G11C2211/4061 ,  G11C2211/4067

摘要： A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memory cells that are refreshed at the same time to permit a relatively slow refresh rate. When transitioning from the full density mode to the half density mode, data are copied from each row of memory cells storing data to an adjacent row of memory cells. The adjacent row of memory cells are made free to store data from an adjacent row by remapping the most significant bit of the row address to the least significant bit of the row address, and then remapping all of the remaining bits of the row address to the next highest order bit.

公开(公告)号：US20050193241A1

公开(公告)日：2005-09-01

申请号：US11108651

申请日：2005-04-11

申请人： Greg Blodgett

发明人： Greg Blodgett

IPC分类号： G11C29/00 ,  G06F11/00

CPC分类号： G11C29/808 ,  G11C29/846

摘要： A block repair device is used in a Dynamic Random Access Memory (DRAM) having a primary array with a defective cell and a redundant array with a redundant row. The block repair device stores a block repair configuration that determines the dimensions (e.g., the number of rows and columns spanned) of a repair block. Routing circuitry is configured by the stored block repair configuration to output some row and column address bits from received row and column addresses in a selected ratio. Comparison circuitry compares the row and column address bits output by the routing circuitry with the address of the defective cell that defines the repair block. When a match occurs, the comparison circuitry implements a block repair by activating the redundant row and by causing data to be written to or read from the activated redundant row instead of the primary array.

摘要翻译： 在具有具有缺陷单元的主阵列和具有冗余行的冗余阵列的动态随机存取存储器（DRAM）中使用块修复装置。 块修复装置存储确定修复块的尺寸（例如，跨越的行和列的数量）的块修复配置。 通过存储的块修复配置来配置路由电路，以从选定的比率的接收的行和列地址输出一些行和列地址位。 比较电路将路由电路输出的行和列地址位与定义修复块的有缺陷单元的地址进行比较。 当匹配发生时，比较电路通过激活冗余行并且通过使数据被写入或从激活的冗余行而不是主阵列读取来实现块修复。

公开(公告)号：US20050116736A1

公开(公告)日：2005-06-02

申请号：US10726312

申请日：2003-12-01

申请人： Greg Blodgett ,  Christopher Morzano

发明人： Greg Blodgett ,  Christopher Morzano

IPC分类号： H03K19/00 ,  H03K19/003

CPC分类号： H03K19/0005

摘要： An off chip driver impedance adjustment circuit includes a storage circuit adapted to receive and store a drive strength adjustment word. A counter circuit is coupled to the storage circuit to receive the drive strength adjustment word and develops a drive strength count responsive to the drive strength adjustment word. A programmable fuse code to preset the counter. An output driver circuit is coupled to the counter circuit to receive the drive strength count and is adapted to receive a data signal. The output driver circuit develops an output signal on an output responsive to the data signal and adjusts a drive strength as a function of the drive strength count.

摘要翻译： 芯片外驱动器阻抗调整电路包括适于接收和存储驱动强度调节字的存储电路。 计数器电路耦合到存储电路以接收驱动强度调节字，并响应于驱动强度调整字产生驱动强度计数。 可编程保险丝代码来预设计数器。 输出驱动器电路耦合到计数器电路以接收驱动强度计数并且适于接收数据信号。 输出驱动器电路根据数据信号在输出端产生输出信号，并根据驱动强度计数调整驱动强度。

公开(公告)号：US07872926B2

公开(公告)日：2011-01-18

申请号：US12492923

申请日：2009-06-26

申请人： Greg Blodgett

发明人： Greg Blodgett

IPC分类号： G11C7/10

CPC分类号： G11C7/1078 ,  G11C7/02 ,  G11C7/1084 ,  G11C11/4093 ,  H03K5/2481

摘要： An input buffer having a comparator that receives an input signal, a reference signal and a positive feedback. The comparator compares the input signal relative to the reference signal and generates an output signal transitioning between a first logic state and a second logic state responsive to the magnitude of the input signal transitioning through the magnitude of the reference signal. The comparator intensifies the output signal in response to the positive feedback from the output of the comparator while the output signal transitions from the first logic state to the second logic state.

摘要翻译： 具有接收输入信号，参考信号和正反馈的比较器的输入缓冲器。 比较器比较输入信号相对于参考信号，并且响应于输入信号的幅度在参考信号的幅度转变而产生在第一逻辑状态和第二逻辑状态之间转换的输出信号。 当输出信号从第一逻辑状态转换到第二逻辑状态时，比较器响应于来自比较器的输出的正反馈增强输出信号。

公开(公告)号：US20090262585A1

公开(公告)日：2009-10-22

申请号：US12492923

申请日：2009-06-26

申请人： Greg Blodgett

发明人： Greg Blodgett

IPC分类号： G11C8/00 ,  H03K19/0175

CPC分类号： G11C7/1078 ,  G11C7/02 ,  G11C7/1084 ,  G11C11/4093 ,  H03K5/2481

摘要： An input buffer having a comparator that receives an input signal, a reference signal and a positive feedback. The comparator compares the input signal relative to the reference signal and generates an output signal transitioning between a first logic state and a second logic state responsive to the magnitude of the input signal transitioning through the magnitude of the reference signal. The comparator intensifies the output signal in response to the positive feedback from the output of the comparator while the output signal transitions from the first logic state to the second logic state.

摘要翻译： 具有接收输入信号，参考信号和正反馈的比较器的输入缓冲器。 比较器比较输入信号相对于参考信号，并且响应于输入信号的幅度在参考信号的幅度转变而产生在第一逻辑状态和第二逻辑状态之间转换的输出信号。 当输出信号从第一逻辑状态转换到第二逻辑状态时，比较器响应于来自比较器的输出的正反馈增强输出信号。

公开(公告)号：US20070171753A1

公开(公告)日：2007-07-26

申请号：US11731058

申请日：2007-03-30

申请人： Donald Morgan ,  Greg Blodgett

发明人： Donald Morgan ,  Greg Blodgett

IPC分类号： G11C7/00

CPC分类号： G11C11/40622 ,  G11C5/14 ,  G11C11/406 ,  G11C11/408 ,  G11C2211/4061 ,  G11C2211/4067

摘要： A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memory cells that are refreshed at the same time to permit a relatively slow refresh rate. When transitioning from the full density mode to the half density mode, data are copied from each row of memory cells storing data to an adjacent row of memory cells. The adjacent row of memory cells are made free to store data from an adjacent row by remapping the most significant bit of the row address to the least significant bit of the row address, and then remapping all of the remaining bits of the row address to the next highest order bit.

摘要翻译： 一种用于以高功率，全密度模式或低功率，半密度模式操作DRAM装置的方法和系统。 在全密度模式下，每个数据位被存储在单个存储器单元中，并且在半密度模式下，每个数据位被存储在同时刷新的两个存储器单元中以允许相对较慢的刷新率。 当从全密度模式转换到半密度模式时，将数据从存储数据的每行存储单元复制到相邻行的存储器单元。 通过将行地址的最高有效位重新映射到行地址的最低有效位，然后将行地址的所有剩余位重新映射到相邻行的相应行的相邻行，使相邻行的存储器单元可以存储来自相邻行的数据 下一个最高位。