公开(公告)号：US08618842B2

公开(公告)日：2013-12-31

申请号：US13249285

申请日：2011-09-30

申请人： Chang Ki Kwon

发明人： Chang Ki Kwon

IPC分类号： H03B1/00 ,  H03K3/00

CPC分类号： H03K5/151 ,  H03K5/1565

摘要： Systems and methods for circuits that self-correct errors due to variations in fabrication processes, voltages, and temperature (PVT), as well as input timing errors. In an exemplary embodiment, a method for improving output signal quality in a complementary logic circuit is provided. An n-type transistor in the complementary logic circuit is digitally enabled or biased with a first variable power supply. A p-type transistor in the complementary logic circuit is digitally enabled or biased with a second variable power supply, providing a voltage different from that of the first variable power supply, to mitigate a difference in the switching times between the p-type transistor and the n-type transistor.

摘要翻译： 由于制造工艺，电压和温度（PVT）的变化以及输入定时误差自校正误差的电路的系统和方法。 在示例性实施例中，提供了一种用于提高互补逻辑电路中的输出信号质量的方法。 互补逻辑电路中的n型晶体管通过第一可变电源数字使能或偏置。 互补逻辑电路中的p型晶体管通过第二可变电源数字使能或偏置，提供与第一可变电源不同的电压，以减轻p型晶体管与 n型晶体管。

公开(公告)号：US08502566B2

公开(公告)日：2013-08-06

申请号：US12125760

申请日：2008-05-22

申请人： Chang Ki Kwon

发明人： Chang Ki Kwon

IPC分类号： H03K5/24

CPC分类号： H03K19/0027 ,  H03K19/018528 ,  H03K19/018585

摘要： A pseudo-differential input receiver is disclosed which is configured to support a wide-range of reference voltage Vref and a wide-range frequency interface with no parallel termination are described herein. The pseudo-differential receiver implementations described herein are very efficient in terms of area, power, and performance. A wide-frequency-range Vref-adjustable input receiver is described herein. The receiver can be configured with a Vref-monitoring PMOS helper FET or an enabled stacked PMOS helper FET to enable the receiver to work at Vref=0V like a conventional CMOS receiver. The receiver can also be configured with a Vref-monitoring NMOS helper FET to enable a Vref-based input receiver to work with programmability on bias currents & trip-point at Vref=(0.5˜0.7)Vdd, depending on the ratio of output driver's impedance and parallel on/off-die termination impedance.

摘要翻译： 公开了一种伪差分输入接收机，其被配置为支持宽范围的参考电压Vref，并且在此描述了没有并行终端的宽范围频率接口。 这里描述的伪差分接收机实现在面积，功率和性能方面是非常有效的。 本文描述了宽频范围Vref可调输入接收机。 接收器可以配置有Vref监控PMOS辅助FET或启用堆叠的PMOS辅助FET，以使接收器能像以前的CMOS接收器一样工作在Vref = 0V。 接收器还可以配置有Vref监控NMOS辅助FET，以使基于Vref的输入接收器能够在Vref =（0.5〜0.7）Vdd的偏置电流和跳变点上进行可编程性处理，具体取决于输出驱动器 阻抗和并联开/关断开端子阻抗。

公开(公告)号：US08238176B2

公开(公告)日：2012-08-07

申请号：US12833744

申请日：2010-07-09

申请人： Chang-Ki Kwon

发明人： Chang-Ki Kwon

IPC分类号： G11C7/00

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/222 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C2207/2254 ,  H03L7/093

摘要： An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines. The first phase mixer is operable to receive the first enable signal and a first delayed enable signal derived from the first enable signal and generate a first signal on the first driver line having a first configurable delay with respect to the first enable signal by mixing the first enable signal and the first delayed enable signal.

摘要翻译： 装置包括端子，第一多个驱动器线和第一相位混合器。 驱动器线路响应于第一使能信号将终端驱动到第一逻辑状态。 第一相混合器耦合到第一组驱动线中的第一相。 第一相位混频器可操作以接收第一使能信号和从第一使能信号导出的第一延迟使能信号，并且在第一驱动线路上产生相对于第一使能信号具有第一可配置延迟的第一信号， 使能信号和第一延迟使能信号。

公开(公告)号：US08063674B2

公开(公告)日：2011-11-22

申请号：US12365559

申请日：2009-02-04

申请人： Chang Ki Kwon ,  Vivek Mohan

发明人： Chang Ki Kwon ,  Vivek Mohan

IPC分类号： H03L7/00 ,  H03L5/00 ,  H03K5/153 ,  H03K19/094

CPC分类号： H03K17/223 ,  G06F1/24 ,  G06F1/26 ,  Y10T307/549

摘要： A multiple supply voltage device includes an input/output (I/O) network operative at a first supply voltage, a core network coupled to the I/O network and operative at a second supply voltage, and a power-on-control (POC) network coupled to the I/O network and the core network. The POC network is configured to transmit a POC signal to the I/O network and includes an adjustable current power up/down detector configured to detect a power state of the core network. The POC network also includes processing circuitry coupled to the adjustable current power up/down detector and configured to process the power state into the POC signal, and one or more feedback circuits. For reducing the leakage current while also improving the power-up/down detection speed, the feedback circuit(s) are coupled to the adjustable current power up/down detector and configured to provide feedback signals to adjust a current capacity of the adjustable current power up/down detector.

摘要翻译： 多电源电压装置包括以第一电源电压工作的输入/输出（I / O）网络，耦合到I / O网络并在第二电源电压下操作的核心网络，以及开机控制（POC ）网络耦合到I / O网络和核心网络。 POC网络被配置为将POC信号发送到I / O网络，并且包括被配置为检测核心网络的电力状态的可调整的当前电力上/下检测器。 POC网络还包括耦合到可调电流功率上/下检测器并被配置为将功率状态处理成POC信号的处理电路以及一个或多个反馈电路。 为了减小泄漏电流同时也提高上电/下电检测速度，反馈电路耦合到可调电流上电/下拉检测器，并被配置为提供反馈信号以调节可调电流功率的电流容量 上/下检测器。

公开(公告)号：US07907928B2

公开(公告)日：2011-03-15

申请号：US11983201

申请日：2007-11-07

申请人： Chang-Ki Kwon ,  Eric Booth

发明人： Chang-Ki Kwon ,  Eric Booth

IPC分类号： H04B1/26

CPC分类号： H03L7/00 ,  G06G7/12 ,  H03K17/00 ,  H03L7/0814

摘要： The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a series connected second transistor responsive to a first clock signal. The unit phase mixer has a pull-down path for pulling the output terminal down to a second voltage. The pull-down path has a third transistor responsive to a second clock signal and a series connected fourth transistor responsive to a second enable signal. The input buffer skews the first and second clock signals by different amounts to enable a break-before-make method of operation so that the first voltage is not connected to the second voltage. The unit phase mixer can be used as a building block in more complex mixers which may include the ability to weight the input clocks as well as providing feed-forward paths for certain of the signals. Because of the rules governing abstract, this abstract should not be used to construe the claims.

摘要翻译： 本公开涉及与输入缓冲器组合的单位相混合器。 单相混合器具有用于将输出端拉至第一电压的上拉路径。 所述上拉路径具有响应于第一使能信号的第一晶体管和响应于第一时钟信号的串联连接的第二晶体管。 单相混合器具有用于将输出端子向下拉到第二电压的下拉路径。 所述下拉路径具有响应于第二时钟信号的第三晶体管和响应于第二使能信号的串联连接的第四晶体管。 输入缓冲器使第一和第二时钟信号偏移不同的量，以使得能够进行先前的断开操作方法，使得第一电压不连接到第二电压。 单相混频器可以用作更复杂的混频器中的构建块，其可以包括对输入时钟加权的能力以及为某些信号提供前馈路径。 由于抽象的规则，本摘要不应用于解释索赔。

公开(公告)号：US07521967B2

公开(公告)日：2009-04-21

申请号：US11881262

申请日：2007-07-26

申请人： Chang Ki Kwon ,  Greg Blodgett

发明人： Chang Ki Kwon ,  Greg Blodgett

IPC分类号： H03K19/0175

CPC分类号： H03L7/00 ,  H03K19/00346

摘要： Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which the data segment is transmitted in response to the plurality of data segments that the other drivers will transmit. The adjustment may compensate for simultaneous switching noise and cross-talk by, for example, delaying the transmission of a data segment or changing the slew rate of the signal carrying the data segment.

摘要翻译： 用于控制驱动器以减少数据相关噪声的技术，例如同时切换效果和串扰效应。 多个驱动器可以各自接收要发送的数据段和其他驱动器将发送的多个数据段。 驱动器控制器可以响应于其他驱动器将要发送的多个数据段来调整发送数据段的时间。 调整可以通过例如延迟数据段的传输或改变携带数据段的信号的转换速率来补偿同时的开关噪声和串扰。

公开(公告)号：US20090051391A1

公开(公告)日：2009-02-26

申请号：US12125760

申请日：2008-05-22

申请人： Chang Ki Kwon

发明人： Chang Ki Kwon

IPC分类号： H03K5/24

CPC分类号： H03K19/0027 ,  H03K19/018528 ,  H03K19/018585

摘要： A pseudo-differential input receiver is disclosed which is configured to support a wide-range of reference voltage Vref and a wide-range frequency interface with no parallel termination are described herein. The pseudo-differential receiver implementations described herein are very efficient in terms of area, power, and performance. A wide-frequency-range Vref-adjustable input receiver is described herein. The receiver can be configured with a Vref-monitoring PMOS helper FET or an enabled stacked PMOS helper FET to enable the receiver to work at Vref=0V like a conventional CMOS receiver. The receiver can also be configured with a Vref-monitoring NMOS helper FET to enable a Vref-based input receiver to work with programmability on bias currents & trip-point at Vref=(0.5˜0.7)Vdd, depending on the ratio of output driver's impedance and parallel on/off-die termination impedance.

摘要翻译： 公开了一种伪差分输入接收机，其被配置为支持宽范围的参考电压Vref，并且在此描述了没有并行终端的宽范围频率接口。 这里描述的伪差分接收机实现在面积，功率和性能方面是非常有效的。 本文描述了宽频范围Vref可调输入接收机。 接收器可以配置有Vref监控PMOS辅助FET或启用堆叠的PMOS辅助FET，以使接收器能像以前的CMOS接收器一样工作在Vref = 0V。 接收器还可以配置有Vref监控NMOS辅助FET，以使基于Vref的输入接收器能够在Vref =（0.5〜0.7）Vdd的偏置电流和跳变点上进行可编程性处理，具体取决于输出驱动器 阻抗和并联开/关断开端子阻抗。

公开(公告)号：US07107476B2

公开(公告)日：2006-09-12

申请号：US10293473

申请日：2002-11-14

申请人： Yong Gwon Jeong ,  Chang Ki Kwon

发明人： Yong Gwon Jeong ,  Chang Ki Kwon

IPC分类号： G06F1/04 ,  G11C8/00 ,  G06F12/00

CPC分类号： G06F13/4243

摘要： A memory system that includes a plurality of memory devices includes: a controller for outputting a first clock signal, a second signal and a plurality of command/address input signals corresponding to the plurality of memory devices, respectively; and a register and delay circuit unit for outputting command/address output signals after receiving the command/address input signals front the controller and then correcting transmission delay due to transmission lines; wherein the plurality of memory devices receive the command/address output signals from the register and delay circuit unit via the transmission lines, respectively, and sample the command/address output signals using the first clock signal directly inputted from the controller. As a result, the memory system can simplify the layout of semiconductor device design and prevent the collision of clocks.

摘要翻译： 包括多个存储器件的存储器系统包括：控制器，分别输出对应于多个存储器件的第一时钟信号，第二信号和多个命令/地址输入信号; 以及寄存器和延迟电路单元，用于在控制器前面接收到命令/地址输入信号，然后校正由于传输线传输的延迟，输出命令/地址输出信号; 其中多个存储器件分别经由传输线从寄存器和延迟电路单元接收命令/地址输出信号，并使用从控制器直接输入的第一时钟信号对命令/地址输出信号进行采样。 结果，存储器系统可以简化半导体器件设计的布局并防止时钟的冲突。

公开(公告)号：US06937111B2

公开(公告)日：2005-08-30

申请号：US10293312

申请日：2002-11-14

申请人： Chang Ki Kwon

发明人： Chang Ki Kwon

IPC分类号： H03K19/0175 ,  H03H11/30 ,  H03K19/0185 ,  H04L25/02 ,  H01P5/12

CPC分类号： H04L25/028 ,  H03K19/018521 ,  H04L25/0278 ,  H04L25/0292

摘要： A transmission line adapter for high speed interface. A receiver receives input signals via a transmission line. An active termination circuit is selectively connected to the transmission line in parallel with the receiver according to a receive condition. A self-terminated driver circuit outputs a first voltage and a second voltage according to output data. A selective circuit for selectively connects the self-terminated driver circuit to the transmission line when output of the self-terminated driver circuit is a first voltage, and selectively connects the self-terminated driver circuit or the active termination circuit to the transmission line when the output is a second voltage.

摘要翻译： 用于高速接口的传输线适配器。 接收机通过传输线接收输入信号。 有源终端电路根据接收条件与接收机并行选择性地连接到传输线。 自终端驱动电路根据输出数据输出第一电压和第二电压。 当自终端驱动电路的输出为第一电压时，选择性地将自终端驱动电路连接到传输线，并且当自终端驱动电路或有源终端电路选择性地连接到传输线时 输出是第二电压。

公开(公告)号：US20130082769A1

公开(公告)日：2013-04-04

申请号：US13249285

申请日：2011-09-30

申请人： Chang Ki Kwon

发明人： Chang Ki Kwon

IPC分类号： H03K17/00

CPC分类号： H03K5/151 ,  H03K5/1565

摘要： Systems and methods for circuits that self-correct errors due to variations in fabrication processes, voltages, and temperature (PVT), as well as input timing errors. In an exemplary embodiment, a method for improving output signal quality in a complementary logic circuit is provided. An n-type transistor in the complementary logic circuit is digitally enabled or biased with a first variable power supply. A p-type transistor in the complementary logic circuit is digitally enabled or biased with a second variable power supply, providing a voltage different from that of the first variable power supply, to mitigate a difference in the switching times between the p-type transistor and the n-type transistor.

摘要翻译： 由于制造工艺，电压和温度（PVT）的变化以及输入定时误差自校正误差的电路的系统和方法。 在示例性实施例中，提供了一种用于提高互补逻辑电路中的输出信号质量的方法。 互补逻辑电路中的n型晶体管通过第一可变电源数字使能或偏置。 互补逻辑电路中的p型晶体管通过第二可变电源数字使能或偏置，提供与第一可变电源不同的电压，以减轻p型晶体管与 n型晶体管。