公开(公告)号：US20050116736A1

公开(公告)日：2005-06-02

申请号：US10726312

申请日：2003-12-01

申请人： Greg Blodgett ,  Christopher Morzano

发明人： Greg Blodgett ,  Christopher Morzano

IPC分类号： H03K19/00 ,  H03K19/003

CPC分类号： H03K19/0005

摘要： An off chip driver impedance adjustment circuit includes a storage circuit adapted to receive and store a drive strength adjustment word. A counter circuit is coupled to the storage circuit to receive the drive strength adjustment word and develops a drive strength count responsive to the drive strength adjustment word. A programmable fuse code to preset the counter. An output driver circuit is coupled to the counter circuit to receive the drive strength count and is adapted to receive a data signal. The output driver circuit develops an output signal on an output responsive to the data signal and adjusts a drive strength as a function of the drive strength count.

摘要翻译： 芯片外驱动器阻抗调整电路包括适于接收和存储驱动强度调节字的存储电路。 计数器电路耦合到存储电路以接收驱动强度调节字，并响应于驱动强度调整字产生驱动强度计数。 可编程保险丝代码来预设计数器。 输出驱动器电路耦合到计数器电路以接收驱动强度计数并且适于接收数据信号。 输出驱动器电路根据数据信号在输出端产生输出信号，并根据驱动强度计数调整驱动强度。

公开(公告)号：US20060125516A1

公开(公告)日：2006-06-15

申请号：US11351047

申请日：2006-02-08

申请人： Greg Blodgett ,  Christopher Morzano

发明人： Greg Blodgett ,  Christopher Morzano

IPC分类号： H03K19/003

CPC分类号： H03K19/0005

摘要： An off chip driver impedance adjustment circuit includes a storage circuit adapted to receive and store a drive strength adjustment word. A counter circuit is coupled to the storage circuit to receive the drive strength adjustment word and develops a drive strength count responsive to the drive strength adjustment word. A programmable fuse code to preset the counter. An output driver circuit is coupled to the counter circuit to receive the drive strength count and is adapted to receive a data signal. The output driver circuit develops an output signal on an output responsive to the data signal and adjusts a drive strength as a function of the drive strength count.

公开(公告)号：US07280410B2

公开(公告)日：2007-10-09

申请号：US11542702

申请日：2006-10-03

申请人： Jeffrey W. Janzen ,  Christopher Morzano

发明人： Jeffrey W. Janzen ,  Christopher Morzano

IPC分类号： G11C7/10

CPC分类号： G11C7/1045 ,  G11C7/1048 ,  G11C11/4096

摘要： A DRAM device includes a mode register that is programmed to select one of two modes for operating data bus terminals in the device. A timing circuit generates timing signals in synchronism with the clock signal that correspond to the selected mode. The timing signals are combined with read data signals to generate corresponding timed read data signals. These timed data signals and termination signals from the timing circuit are applied to pull-up and pull-down circuitry, which drive respective pull-up and pull-down transistors coupled to the data bus terminals. The transistors drive the data bus terminals to either a first or a second voltage if the first mode of operation is selected and to either a third or a fourth voltage if the second mode of operation is selected. Additionally, the pull-up and pull-down transistors bias the data bus terminals to respective voltages corresponding to the selected operating mode.

公开(公告)号：US20070121417A1

公开(公告)日：2007-05-31

申请号：US11698503

申请日：2007-01-26

申请人： Christopher Morzano ,  Jeffrey Wright

发明人： Christopher Morzano ,  Jeffrey Wright

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C11/4087 ,  G11C29/844

摘要： An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location address enable signal, enabling one of a decoder and a redundant decoder in response to the match signal, wherein the decoder is operable to generate a location select signal for selecting a first location, the decoder being responsive to the pre-decoded location address signal, and wherein the redundant decoder is operable to generate a redundant location select signal for selecting a second location, the redundant decoder being responsive to the redundant location address enable signal, and terminating one of the generation of a location select signal and the generation of a redundant location select signal in response to a precharge signal.

公开(公告)号：US20060250163A1

公开(公告)日：2006-11-09

申请号：US11483767

申请日：2006-07-11

申请人： Christopher Morzano

发明人： Christopher Morzano

IPC分类号： H03F3/45

CPC分类号： H03K5/1565 ,  H03K5/151

摘要： The present invention provides a clock signal input circuit that is able to provide inverse internal clock signals generated by the same input buffer as the address and data signals which exhibit reduced skew. When a skewed external noninverse clock signal and a corresponding external inverse clock signal are passed through respective reference voltage input buffers there is no reduction in skew between the two internal signals. In a preferred embodiment, the invention provides back to back inverters connected to both lines carrying the noninverted and inverted internal clock signals. The slower internal clock signal has an extra inverter driving it when it switches states and the faster internal clock signal has an extra inverter fighting it when it switches states. The skew of the two signals is reduced, allowing for faster operation of the integrated circuit and a reduction in misread data signals.

摘要翻译： 本发明提供一种时钟信号输入电路，其能够提供由相同的输入缓冲器产生的逆内部时钟信号，这些信号与表现出减小的偏移的地址和数据信号相反。 当偏斜的外部非反相时钟信号和对应的外部反相时钟信号通过相应的参考电压输入缓冲器时，两个内部信号之间的偏差不会减小。 在一个优选实施例中，本发明提供了连接到两个线路的背靠背的反相器，它们承载了非反相和反相的内部时钟信号。 较慢的内部时钟信号在其切换状态时有一个额外的变频器驱动它，而更快的内部时钟信号在其切换状态时有一个额外的变频器与其作战。 两个信号的偏斜减小，允许集成电路的更快的运行和误读数据信号的减少。

公开(公告)号：US20060007762A1

公开(公告)日：2006-01-12

申请号：US10887616

申请日：2004-07-09

申请人： Christopher Morzano ,  Jeffrey Wright

发明人： Christopher Morzano ,  Jeffrey Wright

IPC分类号： G11C29/00

CPC分类号： G11C8/10 ,  G11C11/4087 ,  G11C29/844

摘要： An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location address enable signal, enabling one of a decoder and a redundant decoder in response to the match signal, wherein the decoder is operable to generate a location select signal for selecting a first location, the decoder being responsive to the pre-decoded location address signal, and wherein the redundant decoder is operable to generate a redundant location select signal for selecting a second location, the redundant decoder being responsive to the redundant location address enable signal, and terminating one of the generation of a location select signal and the generation of a redundant location select signal in response to a precharge signal.

摘要翻译： 一种用于选择存储设备中的存储位置的装置和方法，包括接收预解码位置地址信号，匹配信号和冗余位置地址使能信号中的至少一个，使解码器和冗余解码器之一响应 其中所述解码器可操作以产生用于选择第一位置的位置选择信号，所述解码器响应于所述预解码的位置地址信号，并且其中所述冗余解码器可操作以产生用于 选择第二位置，所述冗余解码器响应于所述冗余位置地址使能信号，并且终止所述产生位置选择信号和响应于预充电信号产生冗余位置选择信号。

公开(公告)号：US07215579B2

公开(公告)日：2007-05-08

申请号：US11061035

申请日：2005-02-18

申请人： Jeffrey W. Janzen ,  Christopher Morzano

发明人： Jeffrey W. Janzen ,  Christopher Morzano

IPC分类号： G11C7/10

CPC分类号： G11C7/1045 ,  G11C7/1048 ,  G11C11/4096

摘要： A DRAM device includes a mode register that is programmed to select one of two modes for operating data bus terminals in the device. A timing circuit generates timing signals in synchronism with the clock signal that correspond to the selected mode. The timing signals are combined with read data signals to generate corresponding timed read data signals. These timed data signals and termination signals from the timing circuit are applied to pull-up and pull-down circuitry, which drive respective pull-up and pull-down transistors coupled to the data bus terminals. The transistors drive the data bus terminals to either a first or a second voltage if the first mode of operation is selected and to either a third or a fourth voltage if the second mode of operation is selected. Additionally, the pull-up and pull-down transistors bias the data bus terminals to respective voltages corresponding to the selected operating mode.

公开(公告)号：US20070036006A1

公开(公告)日：2007-02-15

申请号：US11542702

申请日：2006-10-03

申请人： Jeffrey Janzen ,  Christopher Morzano

发明人： Jeffrey Janzen ,  Christopher Morzano

IPC分类号： G11C7/10

CPC分类号： G11C7/1045 ,  G11C7/1048 ,  G11C11/4096

摘要： A DRAM device includes a mode register that is programmed to select one of two modes for operating data bus terminals in the device. A timing circuit generates timing signals in synchronism with the clock signal that correspond to the selected mode. The timing signals are combined with read data signals to generate corresponding timed read data signals. These timed data signals and termination signals from the timing circuit are applied to pull-up and pull-down circuitry, which drive respective pull-up and pull-down transistors coupled to the data bus terminals. The transistors drive the data bus terminals to either a first or a second voltage if the first mode of operation is selected and to either a third or a fourth voltage if the second mode of operation is selected. Additionally, the pull-up and pull-down transistors bias the data bus terminals to respective voltages corresponding to the selected operating mode.

摘要翻译： DRAM设备包括被编程为选择用于在设备中操作数据总线端子的两种模式之一的模式寄存器。 定时电路产生与对应于所选模式的时钟信号同步的定时信号。 定时信号与读数据信号组合，以产生相应的定时读数据信号。 来自定时电路的这些定时数据信号和终止信号被施加到上拉和下拉电路，其驱动耦合到数据总线端子的相应上拉和下拉晶体管。 如果选择了第一操作模式，则晶体管将数据总线端子驱动为第一或第二电压，并且如果选择了第二操作模式，则晶体管驱动到第三或第四电压。 此外，上拉和下拉晶体管将数据总线端子偏置到对应于所选择的操作模式的相应电压。

公开(公告)号：US20060171219A1

公开(公告)日：2006-08-03

申请号：US11316377

申请日：2005-12-22

申请人： Christopher Morzano ,  Jeffrey Wright

发明人： Christopher Morzano ,  Jeffrey Wright

IPC分类号： G11C29/00

CPC分类号： G11C8/10 ,  G11C11/4087 ,  G11C29/844

摘要： An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location address enable signal, enabling one of a decoder and a redundant decoder in response to the match signal, wherein the decoder is operable to generate a location select signal for selecting a first location, the decoder being responsive to the pre-decoded location address signal, and wherein the redundant decoder is operable to generate a redundant location select signal for selecting a second location, the redundant decoder being responsive to the redundant location address enable signal, and terminating one of the generation of a location select signal and the generation of a redundant location select signal in response to a precharge signal.

摘要翻译： 一种用于选择存储设备中的存储位置的装置和方法，包括接收预解码位置地址信号，匹配信号和冗余位置地址使能信号中的至少一个，使解码器和冗余解码器之一响应 其中所述解码器可操作以产生用于选择第一位置的位置选择信号，所述解码器响应于所述预解码的位置地址信号，并且其中所述冗余解码器可操作以产生用于 选择第二位置，所述冗余解码器响应于所述冗余位置地址使能信号，并且终止所述产生位置选择信号和响应于预充电信号产生冗余位置选择信号。

公开(公告)号：US20060198236A1

公开(公告)日：2006-09-07

申请号：US11398269

申请日：2006-04-05

申请人： Wen Li ,  Christopher Morzano

发明人： Wen Li ,  Christopher Morzano

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C7/1078 ,  G11C7/1093

摘要： Disclosed herein are exemplary embodiments of an improved write address shift register structure useful for example in a DDR3 DRAM having read/write latency. The disclosed shift register structure propagates write addresses from an address bus outside the device to array decoders to allow latent data to be written into the cells in the memory array at a proper time. The register structure comprises a reduced number of registers (e.g., four) thus eliminating the need for extraneous registers which might otherwise be used to propagate “don't care” addresses. The registers are clocked, and the addresses propagated though the registers, in accordance with a latency bus through which a user defines the desired read/write latency in accordance with user preferences and the desired clock speed of the device. The clock for each register is preferably decoded from the latency bus and hence each register preferably has its own unique clock.