公开(公告)号：US07295050B2

公开(公告)日：2007-11-13

申请号：US11117400

申请日：2005-04-29

申请人： Chang-Ho Shin ,  Nam-Jong Kim

发明人： Chang-Ho Shin ,  Nam-Jong Kim

IPC分类号： H03L7/00

CPC分类号： H03K17/223 ,  H03K2217/0036

摘要： A power-up reset circuit with reduced power consumption. The resistance of the power-up reset circuit may be adjusted during a power-up operation. The standby current may thereby be reduced, which may reduce the power consumption in the power-up reset circuit.

摘要翻译： 上电复位电路，功耗降低。 上电复位电路的电阻可以在上电操作期间进行调整。 从而可以减少待机电流，这可能降低上电复位电路中的功耗。

公开(公告)号：US07521988B2

公开(公告)日：2009-04-21

申请号：US11730651

申请日：2007-04-03

申请人： Chang-Ho Shin

发明人： Chang-Ho Shin

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： G11C5/145 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074

摘要： A semiconductor device has a power-saving mode and a normal mode. A voltage booster within the semiconductor device responds to the normal mode and the power-saving mode by controlling various internal operating voltages of the semiconductor device using a level shifter, an internal voltage booster, and a voltage boosting circuit. The initial voltage booster is configured to transmit an external power supply voltage through an initial boosting node to a voltage boosting terminal in response to the level shifter output signal during the normal mode, and to block transmission of the external power supply voltage to the initial boosting node to decrease a voltage level of the initial boosting node during the power-saving mode.

摘要翻译： 半导体器件具有省电模式和正常模式。 半导体器件内的升压器通过使用电平转换器，内部升压器和升压电路控制半导体器件的各种内部工作电压来响应正常模式和功率节省模式。 初始升压器被配置为响应于在正常模式期间的电平移位器输出信号而将外部电源电压通过初始升压节点发送到升压端子，并且阻止外部电源电压发送到初始升压 节点，以在节电模式期间降低初始升压节点的电压电平。

公开(公告)号：US20080171451A1

公开(公告)日：2008-07-17

申请号：US12007735

申请日：2008-01-15

申请人： Chang-Ho Shin ,  Hun Joo Hahm ,  Jung Kyu Park ,  Won Joon Lee ,  Hyung Suk Kim

发明人： Chang-Ho Shin ,  Hun Joo Hahm ,  Jung Kyu Park ,  Won Joon Lee ,  Hyung Suk Kim

IPC分类号： H01R12/00

CPC分类号： H01R12/721 ,  H01R12/52 ,  H01R12/7082 ,  H01R12/732

摘要： There are provided a printed circuit board connector for a backlight unit and a chassis using the same. The printed circuit board connector for a backlight unit including: a horizontal supporter; a vertical supporter having one end connected to the horizontal supporter to divide the horizontal supporter into first and second areas; at least one connecting terminal formed on the horizontal supporter to be partially exposed in each of the first and second areas of the horizontal supporter, wherein the connecting terminal electrically connects printed circuit boards having one ends placed on the first and second areas, respectively.

摘要翻译： 提供了一种用于背光单元的印刷电路板连接器和使用其的底座。 一种用于背光单元的印刷电路板连接器，包括：水平支撑件; 垂直支撑件，其一端连接到水平支撑件，以将水平支撑件分成第一和第二区域; 至少一个形成在所述水平支撑件上的连接端子，以部分地暴露在所述水平支撑件的所述第一和第二区域中的每一个中，其中所述连接端子电连接分别具有放置在所述第一和第二区域上的一端的印刷电路板。

公开(公告)号：US20050280450A1

公开(公告)日：2005-12-22

申请号：US11117400

申请日：2005-04-29

申请人： Chang-Ho Shin ,  Nam-Jong Kim

发明人： Chang-Ho Shin ,  Nam-Jong Kim

IPC分类号： G11C5/14 ,  H03K17/00 ,  H03K17/22 ,  H03L7/00

CPC分类号： H03K17/223 ,  H03K2217/0036

摘要： A power-up reset circuit with reduced power consumption. The resistance of the power-up reset circuit may be adjusted during a power-up operation. The standby current may thereby be reduced, which may reduce the power consumption in the power-up reset circuit.

摘要翻译： 上电复位电路，功耗降低。 上电复位电路的电阻可以在上电操作期间进行调整。 从而可以减少待机电流，这可能降低上电复位电路中的功耗。

公开(公告)号：US07558128B2

公开(公告)日：2009-07-07

申请号：US11473402

申请日：2006-06-24

申请人： Chang-Ho Shin ,  Jong-Hyun Choi

发明人： Chang-Ho Shin ,  Jong-Hyun Choi

IPC分类号： G11C5/14

CPC分类号： G11C5/145 ,  G11C5/147

摘要： A semiconductor memory device includes a cell array internal voltage generating circuit for generating cell array reference voltage and a cell array internal voltage from a first external power voltage, a peripheral circuit internal voltage generating circuit for generating a peripheral circuit reference voltage and a peripheral circuit internal voltage from the first external power voltage, and a voltage boosting circuit power voltage generating circuit for generating a voltage boosting circuit reference voltage and a voltage boosting circuit power voltage from a second external power voltage.

摘要翻译： 一种半导体存储器件，包括用于产生单元阵列参考电压的单元阵列内部电压产生电路和来自第一外部电源电压的单元阵列内部电压，用于产生外围电路参考电压的外围电路内部电压产生电路和外部电路内部电路的外围电路 来自第一外部电源电压的电压，以及用于从第二外部电源电压产生升压电路参考电压和升压电路电源电压的升压电路电源电压产生电路。

公开(公告)号：US20080018381A1

公开(公告)日：2008-01-24

申请号：US11730651

申请日：2007-04-03

申请人： Chang-Ho Shin

发明人： Chang-Ho Shin

IPC分类号： G05F1/10 ,  G11C5/14

CPC分类号： G11C5/145 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074

摘要： A semiconductor device has a power-saving mode and a normal mode. A voltage booster within the semiconductor device responds to the normal mode and the power-saving mode by controlling various internal operating voltages of the semiconductor device using a level shifter, an internal voltage booster, and a voltage boosting circuit. The initial voltage booster is configured to transmit an external power supply voltage through an initial boosting node to a voltage boosting terminal in response to the level shifter output signal during the normal mode, and to block transmission of the external power supply voltage to the initial boosting node to decrease a voltage level of the initial boosting node during the power-saving mode.

摘要翻译： 半导体器件具有省电模式和正常模式。 半导体器件内的升压器通过使用电平转换器，内部升压器和升压电路控制半导体器件的各种内部工作电压来响应正常模式和功率节省模式。 初始升压器被配置为响应于在正常模式期间的电平移位器输出信号而将外部电源电压通过初始升压节点发送到升压端子，并且阻止外部电源电压发送到初始升压 节点，以在节电模式期间降低初始升压节点的电压电平。

公开(公告)号：US20060192607A1

公开(公告)日：2006-08-31

申请号：US11360106

申请日：2006-02-22

申请人： Ki-Chul Chun ,  Chang-Ho Shin

发明人： Ki-Chul Chun ,  Chang-Ho Shin

IPC分类号： G05F1/10

CPC分类号： G11C5/145 ,  H02M1/36 ,  H02M3/073 ,  H02M2003/075

摘要： A boost voltage generating circuit of a semiconductor device includes a main pump circuit having a transfer transistor, the main pump circuit to boost a voltage of a boost node and to transfer charge from the boost node to an output node through the transfer transistor in response to at least one control signal, and an additional pump circuit configured to boost a voltage of a terminal of the transfer transistor.

公开(公告)号：US07576589B2

公开(公告)日：2009-08-18

申请号：US11360106

申请日：2006-02-22

申请人： Ki-Chul Chun ,  Chang-Ho Shin

发明人： Ki-Chul Chun ,  Chang-Ho Shin

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： G11C5/145 ,  H02M1/36 ,  H02M3/073 ,  H02M2003/075

摘要： A boost voltage generating circuit of a semiconductor device includes a main pump circuit having a transfer transistor, the main pump circuit to boost a voltage of a boost node and to transfer charge from the boost node to an output node through the transfer transistor in response to at least one control signal, and an additional pump circuit configured to boost a voltage of a terminal of the transfer transistor.

摘要翻译： 半导体器件的升压电压产生电路包括具有转移晶体管的主泵电路，主泵电路，用于升压升压节点的电压，并响应于所述转换晶体管，通过转移晶体管将电荷从升压节点传送到输出节点 至少一个控制信号，以及被配置为升高转移晶体管的端子的电压的附加泵浦电路。

公开(公告)号：US07348816B2

公开(公告)日：2008-03-25

申请号：US11338202

申请日：2006-01-24

申请人： Chang-Ho Shin

发明人： Chang-Ho Shin

IPC分类号： H03L7/00

CPC分类号： H03K17/223

摘要： In a power-on reset circuit and a method of generating a power-on reset signal tolerant of variation of an ambient temperature, the power-on reset circuit includes a first power-on reset unit, a second power-on reset unit and a logic gate. The first power-on reset unit generates a first power-on reset signal that is activated at a first level of a power supply voltage at a first temperature, and is activated at a second level of the power supply voltage at a second temperature. The second power-on reset unit generates a second power-on reset signal that is activated at the second level at the first temperature, and is activated at the first level at the second temperature. The logic gate executes a logical disjunction operation or a logical conjunction operation of the first power-on reset signal and the second power-on reset signal and generates a third power-on reset signal.

摘要翻译： 在上电复位电路和产生允许环境温度变化的上电复位信号的方法中，上电复位电路包括第一上电复位单元，第二上电复位单元和第二上电复位单元 逻辑门 第一上电复位单元产生在第一温度的电源电压的第一电平下被激活的第一上电复位信号，并且在第二温度的电源电压的第二电平下被激活。 第二上电复位单元产生在第二温度下在第二电平激活的第二上电复位信号，并且在第二温度下在第一电平激活。 逻辑门执行第一上电复位信号和第二上电复位信号的逻辑分离操作或逻辑连接操作，并产生第三上电复位信号。

公开(公告)号：US20060291279A1

公开(公告)日：2006-12-28

申请号：US11473402

申请日：2006-06-24

申请人： Chang-Ho Shin ,  Jong-Hyun Choi

发明人： Chang-Ho Shin ,  Jong-Hyun Choi

IPC分类号： G11C11/34

CPC分类号： G11C5/145 ,  G11C5/147

摘要： A semiconductor memory device includes a cell array internal voltage generating circuit for generating cell array reference voltage and a cell array power voltage from a first external power voltage, a peripheral circuit internal voltage generating circuit for generating a peripheral circuit reference voltage and a peripheral circuit power voltage from the first external power voltage, and a voltage boosting circuit power voltage generating circuit for generating a voltage boosting circuit reference voltage and a voltage boosting circuit power voltage from a second external power voltage.

摘要翻译： 一种半导体存储器件，包括用于从第一外部电源电压产生单元阵列参考电压和单元阵列电源电压的单元阵列内部电压产生电路，用于产生外围电路参考电压的外围电路内部电压产生电路和外围电路电源 来自第一外部电源电压的电压，以及用于从第二外部电源电压产生升压电路参考电压和升压电路电源电压的升压电路电源电压产生电路。