公开(公告)号：US08298843B2

公开(公告)日：2012-10-30

申请号：US12943345

申请日：2010-11-10

申请人： Ki-Chul Chun ,  Hwan Kim ,  Deuk-Soo Jung

发明人： Ki-Chul Chun ,  Hwan Kim ,  Deuk-Soo Jung

IPC分类号： H01L21/00

CPC分类号： H01L27/088 ,  G02F1/136213 ,  G02F1/136227 ,  G02F2201/40 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1288

摘要： An array substrate includes first and second lines on a substrate and formed of a metallic material; a gate electrode connected to the first line; a gate insulating layer on the first and second lines and the gate electrode and including a groove exposing the substrate and positioned between the first and second lines; a semiconductor layer on the gate insulating layer and corresponding to the gate electrode; a data line crossing the first and second lines and on the gate insulating layer; a source electrode connected to the data line; a drain electrode spaced apart from the source electrode; a passivation layer on the data line, the source electrode and the drain electrode and including an opening, the opening exposing the gate insulating layer and the drain electrode; and a pixel electrode positioned on the gate insulating layer and in the opening and contacting the drain electrode.

摘要翻译： 阵列基板在基板上包括由金属材料形成的第一和第二线; 连接到第一线的栅电极; 在第一和第二线路上的栅极绝缘层和栅电极，并且包括暴露衬底并定位在第一和第二线之间的沟槽; 栅极绝缘层上的半导体层，并对应于栅电极; 跨越第一和第二线路以及栅极绝缘层的数据线; 连接到数据线的源电极; 与源电极间隔开的漏电极; 数据线上的钝化层，源电极和漏电极，并且包括开口，所述开口暴露栅极绝缘层和漏电极; 以及位于栅极绝缘层上且位于开口中且与漏电极接触的像素电极。

公开(公告)号：US20080208537A1

公开(公告)日：2008-08-28

申请号：US12037324

申请日：2008-02-26

申请人： Jung-Bae LEE ,  Ki-Chul CHUN

发明人： Jung-Bae LEE ,  Ki-Chul CHUN

IPC分类号： G06F15/00

CPC分类号： G11C29/50 ,  G11C29/50012 ,  G11C2029/1206

摘要： A circuit measuring the operating speed of a semiconductor memory chip in relation to a defined asynchronous access time is disclosed. The circuit includes a test signal path extending between a test input pad and a test output pad and is formed by a plurality of test signal path segments and at least one delay element associated with at least one of the plurality of test signal path segments, such that a delay time for a test signal communicated through the test signal path is indicative of the actual asynchronous access time for the semiconductor memory chip. Each one of the plurality of test signal path segments is either an interior test signal path segment or an exterior test signal path segment.

摘要翻译： 公开了相对于定义的异步访问时间测量半导体存储器芯片的操作速度的电路。 电路包括在测试输入焊盘和测试输出焊盘之间延伸的测试信号路径，并且由多个测试信号路径段和与多个测试信号路径段中的至少一个相关联的至少一个延迟元件形成， 通过测试信号路径传送的测试信号的延迟时间表示半导体存储器芯片的实际异步访问时间。 多个测试信号路径段中的每一个是内部测试信号路径段或外部测试信号路径段。

公开(公告)号：US20070194381A1

公开(公告)日：2007-08-23

申请号：US11708321

申请日：2007-02-21

申请人： Ki-Chul Chun

发明人： Ki-Chul Chun

IPC分类号： H01L23/62

CPC分类号： H01L23/34 ,  G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  G11C11/4074 ,  H01L2924/0002 ,  H01L2924/00

摘要： An example embodiment of the memory integrated circuit device may include a first temperature sensing unit, a first voltage adjusting unit, and a MOS back bias voltage outputting unit. The first voltage adjusting unit may be configured to output a voltage based on an output signal of the temperature sensing unit such that the voltage output changes based on changes in a sensed temperature. The MOS back bias voltage outputting unit may be configured to receive the voltage output by the voltage adjusting unit and configured to output the MOS back bias voltage based on the voltage output by the first voltage adjusting unit.

摘要翻译： 存储器集成电路器件的示例性实施例可以包括第一温度感测单元，第一电压调节单元和MOS背偏置电压输出单元。 第一电压调整单元可以被配置为基于温度感测单元的输出信号输出电压，使得电压输出基于感测温度的变化而改变。 MOS背偏置电压输出单元可以被配置为接收由电压调节单元输出的电压，并且被配置为基于第一电压调节单元输出的电压来输出MOS反向偏置电压。

公开(公告)号：US20060192607A1

公开(公告)日：2006-08-31

申请号：US11360106

申请日：2006-02-22

申请人： Ki-Chul Chun ,  Chang-Ho Shin

发明人： Ki-Chul Chun ,  Chang-Ho Shin

IPC分类号： G05F1/10

CPC分类号： G11C5/145 ,  H02M1/36 ,  H02M3/073 ,  H02M2003/075

摘要： A boost voltage generating circuit of a semiconductor device includes a main pump circuit having a transfer transistor, the main pump circuit to boost a voltage of a boost node and to transfer charge from the boost node to an output node through the transfer transistor in response to at least one control signal, and an additional pump circuit configured to boost a voltage of a terminal of the transfer transistor.

公开(公告)号：US06891767B2

公开(公告)日：2005-05-10

申请号：US10392079

申请日：2003-03-20

申请人： Ki Chul Chun ,  Kyu Chan Lee

发明人： Ki Chul Chun ,  Kyu Chan Lee

IPC分类号： G11C11/41 ,  G11C7/12 ,  G11C7/00

CPC分类号： G11C7/12

摘要： A semiconductor memory device and a method for pre-charging the same, the semiconductor memory device comprising a plurality of memory cell array blocks, each having a plurality of memory cells connected between respective bit line pairs and respective word line pairs, a plurality of pairs of data input/output lines connected to the respective bit line pairs for transferring data, a first pre-charge circuit for pre-charging the bit line pairs to a first pre-charge voltage during a first operation, a second pre-charge circuit for pre-charging the data input/output line pairs and the first pre-charge voltage to the first pre-charge voltage during the first operation, a plurality of third pre-charge circuits, each being disabled in the first operation and pre-charges the data input/output line pairs in the corresponding memory cell array blocks to a second pre-charge voltage during a second operation, and a discharging circuit for lowering the first pre-charge voltage when the first pre-charge voltage is greater than a desired voltage level during the first operation.

摘要翻译： 一种半导体存储器件及其预充电方法，所述半导体存储器件包括多个存储单元阵列块，每个存储单元阵列块具有连接在各位线对与相应字线对之间的多个存储单元，多对 连接到用于传送数据的各个位线对的数据输入/输出线的第一预充电电路，用于在第一操作期间将位线对预充电到第一预充电电压的第一预充电电路， 在第一操作期间将数据输入/输出线对和第一预充电电压预充电到第一预充电电压，多个第三预充电电路，每个在第一操作中被禁用，并且对 相应的存储单元阵列中的数据输入/输出线对在第二操作期间阻塞到第二预充电电压;以及放电电路，用于当第一预充电时降低第一预充电电压 在第一次操作期间，大电压大于期望的电压电平。

公开(公告)号：US07091758B2

公开(公告)日：2006-08-15

申请号：US10834851

申请日：2004-04-30

申请人： Ki-Chul Chun ,  Jae-Yoon Sim

发明人： Ki-Chul Chun ,  Jae-Yoon Sim

IPC分类号： H03K17/22

CPC分类号： H03K3/356008 ,  H03K17/223

摘要： A semiconductor integrated circuit may include an internal circuit, and a power-on reset circuit for generating a power-on reset signal to initialize the internal circuit at a power-on. At the power-on, the power-on reset circuit delays a transition of the power-on reset signal from a first level to a second level until a given time duration after the power supply voltage reaches a detection voltage.

摘要翻译： 半导体集成电路可以包括内部电路和用于产生上电复位信号的上电复位电路，以在通电时初始化内部电路。 在上电时，上电复位电路延迟上电复位信号从第一电平转换到第二电平，直到电源电压达到检测电压之后的给定持续时间。

公开(公告)号：US07079425B2

公开(公告)日：2006-07-18

申请号：US10942829

申请日：2004-09-17

申请人： Ki-Chul Chun

发明人： Ki-Chul Chun

IPC分类号： G11C7/10

CPC分类号： G11C7/1057 ,  G11C7/1045 ,  G11C7/1051

摘要： A semiconductor memory device with a data output circuit that flexibly sets an initial value of a driver strength using fuses.

摘要翻译： 一种具有数据输出电路的半导体存储器件，其使用熔丝灵活地设定驱动器强度的初始值。

公开(公告)号：US20060023535A1

公开(公告)日：2006-02-02

申请号：US11180832

申请日：2005-07-13

申请人： Ki-chul Chun ,  Chang-ho Shin

发明人： Ki-chul Chun ,  Chang-ho Shin

IPC分类号： G11C7/00

CPC分类号： G11C11/4094 ,  G11C7/12

摘要： Provided are a bitline driving circuit of an integrated circuit memory that enhances a precharge scheme and a sense amplification scheme and a bitline driving method. In the bitline driving circuit, a new scheme of precharging the bitlines to voltages greater than or smaller than a voltage VCCA/2 using an auxiliary circuit is used to increase a gate-source voltage of transistors included in each sense amplification circuit. Also, when cell data is 1 and 0, a dummy cell can maintain a voltage difference between the bitlines BL and BLB generated after charge sharing. Furthermore, a sense amplification circuit, which is controlled by an offset control circuit, can remove a threshold voltage offset between the transistors included in each sense amplification circuit. At this time, an auxiliary circuit is used to stabilize the voltage difference.

摘要翻译： 提供了集成电路存储器的位线驱动电路，其增强了预充电方案和感测放大方案和位线驱动方法。 在位线驱动电路中，使用使用辅助电路将位线预充电至大于或小于电压VCCA / 2的电压的新方案用于增加每个读出放大电路中包括的晶体管的栅极 - 源极电压。 此外，当单元数据为1和0时，虚设单元可以维持电荷共享后产生的位线BL和BLB之间的电压差。 此外，由偏移控制电路控制的感测放大电路可以去除每个感测放大电路中包括的晶体管之间的阈值电压偏移。 此时，使用辅助电路来稳定电压差。

公开(公告)号：US06867639B2

公开(公告)日：2005-03-15

申请号：US10648603

申请日：2003-08-25

申请人： Ki-chul Chun

发明人： Ki-chul Chun

IPC分类号： G11C5/14 ,  G05F1/10

CPC分类号： G11C5/147

摘要： A voltage generator for use in a semiconductor memory device provides a stabilized output voltage of half a supply voltage Vcc. The voltage generator includes a reference voltage generator capable of generating first and second reference voltages. A differential amplification drive circuit is capable of generating an output voltage responsive to the first and second reference voltages. A resistance/diode reference voltage generator is capable of generating third and fourth reference voltages. And a pull-up/down drive is capable of changing the output voltage responsive to the third and fourth reference voltages. The resulting voltage generator provides a stable and accurate output voltage that is resistant to output load variations.

摘要翻译： 用于半导体存储器件的电压发生器提供一半电源电压Vcc的稳定输出电压。 电压发生器包括能够产生第一和第二参考电压的参考电压发生器。 差分放大驱动电路能够产生响应于第一和第二参考电压的输出电压。 电阻/二极管参考电压发生器能够产生第三和第四参考电压。 并且上拉/下拉驱动器能够响应于第三和第四参考电压来改变输出电压。 所得到的电压发生器提供稳定和精确的输出电压，耐输出负载变化。

公开(公告)号：US06781891B2

公开(公告)日：2004-08-24

申请号：US10349386

申请日：2003-01-21

申请人： Ki-Chul Chun

发明人： Ki-Chul Chun

IPC分类号： G11C700

CPC分类号： G05F1/10 ,  G11C5/14 ,  G11C11/407 ,  H01L21/822 ,  H01L27/04

摘要： The present invention relates to a half power supply voltage generating circuit and a semiconductor memory device having the same. The half power supply voltage generating circuit according to the present invention includes components that allow it to operate regardless of whether the power supply falls below a threshold voltage of included MOS transistors.

摘要翻译： 本发明涉及半电源电压产生电路和具有该半电源电压产生电路的半导体存储器件。 根据本发明的半电源电压产生电路包括允许其工作的组件，而不管电源是否低于包含的MOS晶体管的阈值电压。