公开(公告)号：US07878858B1

公开(公告)日：2011-02-01

申请号：US12833034

申请日：2010-07-09

申请人： Chang-Hsien Tung ,  Tzu-Ching Tsai ,  Kuo-Chun Hsu

发明人： Chang-Hsien Tung ,  Tzu-Ching Tsai ,  Kuo-Chun Hsu

IPC分类号： H01R24/00

CPC分类号： H01R27/00 ,  G06K7/0021

摘要： An N-in-1 card connector (100), used for receiving at least two cards (a MS card A and a SD card B), includes an insulative housing (10), a number of first terminals (40) retained in the insulative housing, an ejector comprising a slider (30) moveably attached to the insulative housing, a floating member (60) floatingly received in the insulative housing and a plurality of second terminals (50) having respective parts retained with the floating member. The floating member remains at a lower position to stay clear of a first, narrower card (A) and is moveable to an upper position by a second, wider card (B). The second terminals are moveable together with the floating member at the upper position for engaging the second card.

摘要翻译： 用于接收至少两张卡（MS卡A和SD卡B）的N合1卡连接器（100）包括绝缘壳体（10），多个第一终端（40）保留在 绝缘壳体，包括可移动地附接到所述绝缘壳体的滑块（30）的顶出器，浮动接纳在所述绝缘壳体中的浮动构件（60）以及具有与所述浮动构件保持的各个部分的多个第二端子（50）。 浮动部件保持在较低位置，以避开第一较窄的卡（A），并可通过第二较宽的卡（B）移动到上部位置。 第二端子可与浮动部件一起在上部位置移动以接合第二卡。

公开(公告)号：US07980870B2

公开(公告)日：2011-07-19

申请号：US12842079

申请日：2010-07-23

申请人： Chang-Hsien Tung ,  Tzu-Ching Tsai ,  Kai-Li Wang

发明人： Chang-Hsien Tung ,  Tzu-Ching Tsai ,  Kai-Li Wang

IPC分类号： H01R13/62

CPC分类号： H01R27/00 ,  G06K13/08 ,  H01R12/721 ,  H01R13/6581

摘要： An electrical card connector (100) includes an insulative housing (10) defining a card receiving room, at least one set of terminals (30) retained in the insulative housing, and an ejector attached on the insulative housing. Each terminal has a soldering portion (303) extending out of the insulative housing and a contacting portion (301) extending towards the card receiving room. The ejector includes a slider (50), at least one spring member (90) and at least one pin member (80) cammedly pushing an inserted card. The slider includes a base portion (501) pressing against the contacting portions of the terminals and a pair of arm portions (503) extending laterally from the base portion. The base portion defines a number of passageways (502) and forms a number of protrusions (5011) extending into the corresponding passageways. The slider blocks the contacting portions from entering the card receiving room at an original position and moves to an inner position for giving way for the contacting portions. The contacting portions extend through the passageways into the card receiving room are supported by the protrusions.

摘要翻译： 电卡连接器（100）包括限定卡接收室的绝缘壳体（10），保持在绝缘壳体中的至少一组端子（30）和连接在绝缘壳体上的喷射器。 每个端子具有从绝缘壳体延伸出的焊接部分（303）和朝向卡接收室延伸的接触部分（301）。 喷射器包括滑块（50），至少一个弹簧构件（90）和至少一个销构件（80），凸出地推动插入的卡。 滑块包括：压靠端子的接​​触部分的基部（501）和从基部侧向延伸的一对臂部（503）。 基部限定多个通道（502）并形成延伸到相应通道中的多个突起（5011）。 滑块阻止接触部分在原始位置进入卡接收室，并移动到用于接触部分的通路的内部位置。 接触部分延伸通过插入卡片容纳室的通道由突起支撑。

公开(公告)号：US07892035B2

公开(公告)日：2011-02-22

申请号：US12542714

申请日：2009-08-18

申请人： Tzu-Ching Tsai ,  Kuo-Chun Hsu

发明人： Tzu-Ching Tsai ,  Kuo-Chun Hsu

IPC分类号： H01R24/00

CPC分类号： H01R12/714 ,  H01R12/721 ,  H01R13/6594 ,  H01R27/02 ,  Y10S439/946

摘要： An electrical card connector includes a first insulative housing (1), a number of first contacts (2) mounted in the first housing and having a first soldering portion (22), a second insulative housing (4) located behind the first housing, a number of second contacts (5) mounted in the second housing and having a second soldering portion (51), and a shell (6) covering the first housing and the second housing. The first housing and the second housing is separated each other. A gap (9) is formed between the shell and the second housing. The second housing with the second contacts moves around the gap, corresponding to the first housing, and then the second soldering portion is adjusted, the first soldering portion and the second soldering portion are in coplanar, and soldered on the PCB without missing.

摘要翻译： 电卡连接器包括第一绝缘壳体（1），安装在第一壳体中并具有第一焊接部分（22）的多个第一触头（2），位于第一壳体后面的第二绝缘壳体（4） 安装在第二壳体中并具有第二焊接部分（51）的第二触点（5）的数量，以及覆盖第一壳体和第二壳体的壳体（6）。 第一壳体和第二壳体彼此分离。 在壳体和第二壳体之间形成间隙（9）。 具有第二触头的第二壳体围绕第一壳体的间隙移动，然后调整第二焊接部分，第一焊接部分和第二焊接部分共面，并且焊接在PCB上而不丢失。

公开(公告)号：US07982315B2

公开(公告)日：2011-07-19

申请号：US12165587

申请日：2008-06-30

申请人： Yinan Chen ,  Hsien-Wen Liu ,  Tzu-Ching Tsai

发明人： Yinan Chen ,  Hsien-Wen Liu ,  Tzu-Ching Tsai

IPC分类号： H01L23/48

CPC分类号： H01L23/53295 ,  H01L21/76831 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided. An amorphous silicon layer that acts as a UV blocking layer replaces a conventional silicon-rich oxide (SRO) layer or the super silicon-rich oxide (SSRO) layer. By doing this, the process window is increased. In addition, silicon nitride sidewall spacer is formed inside the contact hole to prevent charge loss.

摘要翻译： 提供半导体器件。 作为UV阻挡层的非晶硅层代替常规富硅氧化物（SRO）层或超富硅氧化物（SSRO）层。 通过这样做，过程窗口增加。 此外，在接触孔内部形成氮化硅侧壁间隔物，以防止电荷损失。

公开(公告)号：US07500879B2

公开(公告)日：2009-03-10

申请号：US11986194

申请日：2007-11-20

申请人： Chien-Jen Ting ,  Tzu-Ching Tsai

发明人： Chien-Jen Ting ,  Tzu-Ching Tsai

IPC分类号： H01R24/00

CPC分类号： H01R12/7029 ,  H01R13/6595

摘要： An electrical card connector includes a metal shield (2), an insulated housing (3) and a terminal module (4). The metal shield defines a receiving room, in which a memory card is insertable in a card inserting direction through an insert opening generally at a front end thereof. The insulated housing is shielded by the metal shield, and defines a receiving portion (34) extending therethrough and adjacent to a rear end thereof. The terminal module is received in the receiving portion of the insulated housing and comprises a pair of locking boards (44) assembling the terminal module on a printed circuit board (5). A plurality of terminals (31) are insert-molded in the terminal module for electrical connection to the memory card.

摘要翻译： 电卡连接器包括金属屏蔽（2），绝缘外壳（3）和端子模块（4）。 金属屏蔽限定了接收室，其中存储卡可以通过大致在其前端处的插入开口插入卡插入方向。 绝缘壳体被金属屏蔽件屏蔽，并且限定了延伸穿过其并与其后端相邻的接收部分（34）。 端子模块被容纳在绝缘壳体的接收部分中，并且包括将终端模块组装在印刷电路板（5）上的一对锁定板（44）。 多个端子（31）被插入模制在端子模块中以与存储卡电连接。

公开(公告)号：US07341952B2

公开(公告)日：2008-03-11

申请号：US11348626

申请日：2006-02-07

申请人： Kaan-Lu Tzou ,  Tzu-Ching Tsai ,  Yi-Nan Chen

发明人： Kaan-Lu Tzou ,  Tzu-Ching Tsai ,  Yi-Nan Chen

IPC分类号： H01L21/302

CPC分类号： H01L27/1087 ,  C03C15/00 ,  H01L21/0332 ,  H01L21/3081

摘要： A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.

摘要翻译： 一种用于蚀刻衬底中的深沟槽的方法。 形成覆盖在基板上的多层硬掩模结构，其包括第一硬掩模层和设置在其上的至少一个第二硬掩模层。 第一硬掩模层由第一硼硅酸盐玻璃（BSG）层和上覆的第一未掺杂硅玻璃（USG）层组成，第二硬质掩模层由第二BSG层和第二USG层组成。 形成覆盖多层硬掩模结构的多晶硅层，然后蚀刻以形成其中的开口。 连续蚀刻多层硬掩模结构和开口下方的底层基板，同时在衬底中形成深沟槽并去除多晶硅层。 去除多层硬掩模结构。

公开(公告)号：US20060118886A1

公开(公告)日：2006-06-08

申请号：US11338330

申请日：2006-01-23

申请人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hui-Min Mao

发明人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hui-Min Mao

IPC分类号： H01L29/772

CPC分类号： H01L21/76897 ,  H01L21/76829 ,  H01L21/76895

摘要： A method of forming a bit line contact via. The method includes providing a substrate having a transistor with a gate electrode, drain region, and source region, forming a conductive layer overlying the drain region, conformally forming an insulating barrier layer overlying the substrate, blanketly forming a dielectric layer overlying the insulating barrier layer, and forming a via through the dielectric layer and insulating barrier layer, exposing the conductive layer.

摘要翻译： 形成位线接触通孔的方法。 该方法包括提供具有晶体管的衬底，该晶体管具有栅极，漏极区和源极区，形成覆盖漏极区的导电层，保形地形成覆盖衬底的绝缘阻挡层，覆盖在绝缘阻挡层上的绝缘层 并且通过介电层和绝缘阻挡层形成通孔，暴露导电层。

公开(公告)号：US06815356B2

公开(公告)日：2004-11-09

申请号：US10379445

申请日：2003-03-03

申请人： Tzu-Ching Tsai ,  Hsin-Jung Ho ,  Yi-Nan Chen

发明人： Tzu-Ching Tsai ,  Hsin-Jung Ho ,  Yi-Nan Chen

IPC分类号： H01L21311

CPC分类号： H01L21/76232 ,  H01L27/1087 ,  H01L29/66181

摘要： A method for forming a bottle trench in a substrate having a pad structure and a trench. First, a first insulating layer is formed in the trench, and a portion of the first insulating layer is removed to a certain depth of the trench. Next, a second insulating layer is formed in the trench, and portions of the second insulating layer on the pad structure and the sidewalls of the trench are removed. Next, an etching stop layer is formed in the trench, and a bottom portion of the etching stop layer is removed. Finally, the etching stop layer is used as a mask to remove the remaining second insulating layer and the first insulating layer.

摘要翻译： 一种在具有衬垫结构和沟槽的衬底中形成瓶沟槽的方法。 首先，在沟槽中形成第一绝缘层，并且将第一绝缘层的一部分去除到沟槽的一定深度。 接下来，在沟槽中形成第二绝缘层，并且去除衬垫结构上的第二绝缘层的部分和沟槽的侧壁。 接下来，在沟槽中形成蚀刻停止层，去除蚀刻停止层的底部。 最后，将蚀刻停止层用作掩模以去除剩余的第二绝缘层和第一绝缘层。

公开(公告)号：US06696344B1

公开(公告)日：2004-02-24

申请号：US10384947

申请日：2003-03-10

申请人： Shian-Jyh Lin ,  Hsin-Jung Ho ,  Chao-Sung Lai ,  Tzu-Ching Tsai

发明人： Shian-Jyh Lin ,  Hsin-Jung Ho ,  Chao-Sung Lai ,  Tzu-Ching Tsai

IPC分类号： H01L218242

CPC分类号： H01L27/1087

摘要： A method for forming a bottle-shaped trench. A semiconductor substrate having a pad stack layer thereon and a trench in a predetermined position is provided. A first dielectric layer is then formed on the lower sidewalls of the trench. Next, a second dielectric layer is formed to cover the upper sidewalls of the trench and the pad stack layer. Then, a protection layer is formed on the sidewalls portions of the second dielectric layer. The first dielectric layer is then removed to expose the lower portion of trench. Wet stripping is then carried out to increase the radius of the lower portion of the trench thereby forming a bottle-shaped trench.

摘要翻译： 一种用于形成瓶形沟槽的方法。 提供其上具有衬垫叠层的半导体衬底和处于预定位置的沟槽。 然后在沟槽的下侧壁上形成第一电介质层。 接下来，形成第二电介质层以覆盖沟槽和衬垫叠层层的上侧壁。 然后，在第二电介质层的侧壁部分上形成保护层。 然后去除第一电介质层以暴露沟槽的下部。 然后进行湿剥离以增加沟槽下部的半径，从而形成瓶形沟槽。

公开(公告)号：US20130102123A1

公开(公告)日：2013-04-25

申请号：US13276960

申请日：2011-10-19

申请人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/02

CPC分类号： H01L27/10867

摘要： A method for manufacturing a buried-strap includes: forming a trench capacitor structure in a semiconductor substrate, wherein the trench capacitor structure has a doped polysilicon layer and an isolation collar covered by the doped polysilicon layer, and a top surface of the doped polysilicon layer is lower than a top surface of the semiconductor substrate such that a first recess is formed; sequentially forming a first resist layer, a second resist layer and a third resist layer over the semiconductor substrate; sequentially patterning the third resist layer, the second resist layer and the first resist layer, forming a patterned tri-layer resist layer over the semiconductor substrate; partially removing a portion of the doped polysilicon layer exposed by the patterned tri-layer resist layer to form a second recess; removing the patterned tri-layer resist layer; and forming an insulating layer in the second recess and a portion of the first recess.

摘要翻译： 一种掩埋带的制造方法包括：在半导体衬底中形成沟槽电容器结构，其中沟槽电容器结构具有掺杂多晶硅层和由掺杂多晶硅层覆盖的隔离环，以及掺杂多晶硅层的顶表面 低于半导体衬底的顶表面，从而形成第一凹槽; 在半导体衬底上依次形成第一抗蚀剂层，第二抗蚀剂层和第三抗蚀剂层; 顺序地图案化第三抗蚀剂层，第二抗蚀剂层和第一抗蚀剂层，在半导体衬底上形成图案化的三层抗蚀剂层; 部分地去除由图案化的三层抗蚀剂层暴露的部分掺杂多晶硅层以形成第二凹槽; 去除图案化的三层抗蚀剂层; 以及在所述第二凹部中形成绝缘层和所述第一凹部的一部分。