公开(公告)号：US20080025392A1

公开(公告)日：2008-01-31

申请号：US11880969

申请日：2007-07-25

申请人： Chang-Hyun Lee ,  Jae-Seok Kim ,  Seong-Joo Lee ,  Yun-Je Oh ,  Young-Hun Joo

发明人： Chang-Hyun Lee ,  Jae-Seok Kim ,  Seong-Joo Lee ,  Yun-Je Oh ,  Young-Hun Joo

IPC分类号： H04N7/26

CPC分类号： H04N19/86 ,  H04N19/115 ,  H04N19/124 ,  H04N19/142 ,  H04N19/61

摘要： A method and apparatus for controlling a video encoding data rate in real-time in order to minimize performance deterioration, even when a scene change has occurred in an application field having a small number of available bits due to a low bit rate and a high frame rate. The method includes: a first step of determining whether scene change has occurred in a current frame; a second step of determining whether a number of current available bits is more than a preset reference when it is determined that the scene change has occurred; and a third step of adjusting a Quantization Parameter (QP) according to a first preset condition when it is determined that the number of current available bits is more than that preset reference. An apparatus includes an encoder QP controller having a QP module for adjusting the QP.

摘要翻译： 即使当由于低比特率和高帧而在具有少量可用比特的应用领域中发生场景变化时，也可以实时地控制视频编码数据速率以便最小化性能劣化的方法和装置 率。 该方法包括：确定在当前帧中是否发生场景变化的第一步骤; 当确定出现场景变化时，确定当前可用位数是否大于预设参考值的第二步骤; 以及当确定当前可用位的数量大于该预设参考值时，根据第一预设条件调整量化参数（QP）的第三步骤。 一种装置包括具有用于调整QP的QP模块的编码器QP控制器。

公开(公告)号：US20080025401A1

公开(公告)日：2008-01-31

申请号：US11880203

申请日：2007-07-20

申请人： Chang-Hyun Lee ,  Jae-Seok Kim ,  Seong-Joo Lee ,  Yun-Je Oh ,  Young-Hun Joo

发明人： Chang-Hyun Lee ,  Jae-Seok Kim ,  Seong-Joo Lee ,  Yun-Je Oh ,  Young-Hun Joo

IPC分类号： H04N7/12

CPC分类号： H04N19/152 ,  H04N19/115 ,  H04N19/124 ,  H04N19/137 ,  H04N19/139 ,  H04N19/176 ,  H04N19/46 ,  H04N19/513 ,  H04N19/61

摘要： A method for measuring an real-time image complexity of an image processed for each macroblock based on a frame includes: identifying a state of a preset value among header bits of information processed for each macroblock in a preceding frame; identifying a state of the preset value among header bits of information processed for each macroblock up to a preceding frame; and detecting image complexity of a current frame through comparison of the identified states.

摘要翻译： 一种用于测量基于帧的每个宏块处理的图像的实时图像复杂度的方法包括：识别针对前一帧中的每个宏块处理的信息的标题位之间的预设值的状态; 识别针对每个宏块处理的信息的标题位之前的预设值的状态，直到前一帧; 并且通过比较所识别的状态来检测当前帧的图像复杂度。

公开(公告)号：US20080025402A1

公开(公告)日：2008-01-31

申请号：US11880205

申请日：2007-07-20

申请人： Chang-Hyun Lee ,  Jae-Seok Kim ,  Seong-Joo Lee ,  Yun-Je Oh ,  Young-Hun Joo

发明人： Chang-Hyun Lee ,  Jae-Seok Kim ,  Seong-Joo Lee ,  Yun-Je Oh ,  Young-Hun Joo

IPC分类号： H04N7/12

CPC分类号： H04N19/103 ,  H04N19/137 ,  H04N19/142 ,  H04N19/172 ,  H04N19/87

摘要： A method of detecting scene conversion in real time for controlling a video encoding data rate, includes: estimating PSNR (Peak Signal to Noise Ratio) of a current frame by using error information between the current frame and the previous frame(a reference frame); determining whether the estimated PSNR escapes a predetermined reference value; and considering that the scene conversion is performed in the current frame when the estimated PSNR escapes the predetermined reference value.

摘要翻译： 一种用于控制视频编码数据速率的实时检测场景转换的方法包括：通过使用当前帧与先前帧（参考帧）之间的误差信息来估计当前帧的PSNR（峰值信噪比）; 确定估计的PSNR是否逃避预定的参考值; 并且考虑到当估计的PSNR逃避预定参考值时，在当前帧中执行场景转换。

公开(公告)号：US07012951B2

公开(公告)日：2006-03-14

申请号：US09871995

申请日：2001-05-31

申请人： Ik-Soo Eo ,  Kyung-Soo Kim ,  Seong-Joo Lee ,  Jae-Seok Kim

发明人： Ik-Soo Eo ,  Kyung-Soo Kim ,  Seong-Joo Lee ,  Jae-Seok Kim

IPC分类号： H04K1/00

CPC分类号： H04B1/7115 ,  H04B1/7117 ,  H04B2201/70707

摘要： A symbol combining method in a Rake receiver, which relates to a method for combining the demodulated multi-path signals in a demodulation process of a code division multiple access communication system. The symbol combining method, a Rake receiver using the symbol combining method and a method for driving the Rake receiver, remarkably reduce a hardware complexity of a FIFO register used to regulate a timing synchronization of each finger in Rake receiver by using a new algorithm in a combining process when a CDMA communication system combines a plurality of multi-path signals therebetween. Whereas a conventional combining algorithm uses an individual FIFO register every finger so as to adjust a timing synchronization of each symbol before combining a demodulated symbol, the inventive combining algorithm performs a symbol combining operation as well as a timing synchronization of a symbol at the same time, and performs a combining action by using only one FIFO register irrespective of the number of fingers.

公开(公告)号：US08652910B2

公开(公告)日：2014-02-18

申请号：US13438250

申请日：2012-04-03

申请人： Bo-Kyeong Kang ,  Jae-Seok Kim ,  Ho-Young Kim ,  Bo-Un Yoon ,  Il-Young Yoon

发明人： Bo-Kyeong Kang ,  Jae-Seok Kim ,  Ho-Young Kim ,  Bo-Un Yoon ,  Il-Young Yoon

IPC分类号： H01L21/336

CPC分类号： H01L21/823431 ,  H01L21/845

摘要： In a method for fabricating a semiconductor device, a substrate may be provided that includes: a base, an active fin that projects from an upper surface of the base and is integrally formed with the base, and a buffer oxide film pattern formed on the active fin in contact with the active fin. A first dummy gate film may be formed on the substrate to cover the buffer oxide film pattern and the first dummy gate film may be smoothed to expose the buffer oxide film pattern. A second dummy gate film may be formed on the exposed buffer oxide film pattern and the first dummy gate film.

摘要翻译： 在制造半导体器件的方法中，可以提供一种基板，其包括：底座，从基座的上表面突出并与基座一体形成的活动翅片，以及形成在活动件上的缓冲氧化膜图案 翅片与活动翅片接触。 可以在衬底上形成第一伪栅极膜以覆盖缓冲氧化膜图案，并且可以平滑第一伪栅极膜以暴露缓冲氧化膜图案。 可以在暴露的缓冲氧化膜图案和第一伪栅极膜上形成第二伪栅极膜。

公开(公告)号：US08470663B2

公开(公告)日：2013-06-25

申请号：US13048683

申请日：2011-03-15

申请人： Seong-Kyu Yun ,  Jae-Seok Kim

发明人： Seong-Kyu Yun ,  Jae-Seok Kim

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/31053 ,  H01L21/823814 ,  H01L21/823828 ,  H01L23/544 ,  H01L29/7848 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of manufacturing a semiconductor device include forming integrated structures of polysilicon patterns and hard mask patterns on a substrate divided into at least an NMOS forming region and a PMOS forming region. A first preliminary insulating interlayer is formed on the integrated structures. A first polishing of the first preliminary insulating interlayer is performed until at least one upper surface of the hard mask patterns is exposed, to form a second preliminary insulating interlayer. The second preliminary insulating interlayer is etched until the upper surfaces of the hard mask patterns are exposed, to form a third preliminary insulating interlayer. A second polishing of the hard mask patterns and the third preliminary insulating interlayer is performed until the polysilicon patterns are exposed to form an insulating interlayer. The polysilicon patterns are removed to form an opening. A metal material is deposed to form a gate electrode pattern in the opening.

摘要翻译： 制造半导体器件的方法包括在分成至少NMOS形成区域和PMOS形成区域的衬底上形成多晶硅图案和硬掩模图案的集成结构。 在集成结构上形成第一初步绝缘中间层。 执行第一初步绝缘中间层的第一次抛光，直到暴露硬掩模图案的至少一个上表面，以形成第二预绝缘中间层。 蚀刻第二初步绝缘中间层直到硬掩模图案的上表面露出，以形成第三初步绝缘中间层。 执行硬掩模图案和第三预备绝缘中间层的第二次抛光，直到多晶硅图案暴露以形成绝缘中间层。 去除多晶硅图形以形成开口。 金属材料被放弃以在开口中形成栅极电极图案。

公开(公告)号：US08437260B2

公开(公告)日：2013-05-07

申请号：US12397876

申请日：2009-03-04

申请人： Ji-Ho Kim ,  Jae-Do Roh ,  Jae-Seok Kim ,  Sang-Min Lee ,  Yun-Ho Jung

发明人： Ji-Ho Kim ,  Jae-Do Roh ,  Jae-Seok Kim ,  Sang-Min Lee ,  Yun-Ho Jung

IPC分类号： H04J1/16

CPC分类号： H04W16/14

摘要： A victim system detector for detecting whether a second wireless communication system uses frequency bands that are used by a first wireless communication system (detecting whether the second wireless communication system is a victim system) includes a correlator and a decision unit. The correlator calculates a correlation value between a frequency domain baseband signal associated with the first wireless communication system and a correlation sequence of the second wireless communication system. The decision unit determines, based on the correlation value, whether the second wireless communication system is a victim system. Therefore, the victim system is detected accurately and efficiently.

摘要翻译： 一种用于检测第二无线通信系统是否使用由第一无线通信系统使用的频带（检测第二无线通信系统是否是受害系统）的受害系统检测器，包括相关器和判定单元。 相关器计算与第一无线通信系统相关联的频域基带信号与第二无线通信系统的相关序列之间的相关值。 决定单元基于相关值来确定第二无线通信系统是否是受害者系统。 因此，准确有效地检测受害者系统。

公开(公告)号：US20070254564A1

公开(公告)日：2007-11-01

申请号：US10580617

申请日：2005-02-16

申请人： Eu-Gene Song ,  Ju-Yeol Lee ,  Sung-Min Kim ,  Jae-Seok Kim ,  Hyun-Woo Lee

发明人： Eu-Gene Song ,  Ju-Yeol Lee ,  Sung-Min Kim ,  Jae-Seok Kim ,  Hyun-Woo Lee

IPC分类号： B24D11/00

CPC分类号： B24D11/02 ,  B24B37/22

摘要： Disclosed is a base pad of polishing pad, which is used in conjunction with polishing slurry during a chemical-mechanical polishing or planarizing process, and a multilayer pad using the same. Since the base pad according to the present invention does not have fine pores, it is possible to prevent premeation of polishing slurry and water and to avoid nonuniformity of physical properties. Thereby, it is possible to lengthen the lifetime of the polishing pad.

摘要翻译： 公开了一种在化学机械抛光或平面化处理过程中与抛光浆料结合使用的抛光垫的基垫，以及使用其的多层垫。 由于根据本发明的基底垫不具有细孔，因此可以防止研磨浆料和水的前体化，并且避免物理性能的不均匀性。 由此，可以延长抛光垫的寿命。

公开(公告)号：US08399327B2

公开(公告)日：2013-03-19

申请号：US13240560

申请日：2011-09-22

申请人： Jong-Won Lee ,  Jae-Seok Kim ,  Bo-Un Yoon

发明人： Jong-Won Lee ,  Jae-Seok Kim ,  Bo-Un Yoon

IPC分类号： H01L21/336

CPC分类号： H01L21/823842 ,  H01L21/823437 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7835

摘要： A method includes forming a plurality of dummy gate structures on a substrate, each dummy gate structure including a dummy gate electrode and a dummy gate mask, forming a first insulation layer on the substrate and the dummy gate structures to fill a first space between the dummy gate structures, planarizing upper portions of the first insulation layer and the dummy gate structures, removing the remaining first insulation layer to expose a portion of the substrate, forming an etch stop layer on the remaining dummy gate structures and the exposed portion of the substrate, forming a second insulation layer on the etch stop layer to fill a second space between the dummy gate structures, planarizing upper portions of the second insulation layer and the etch stop layer to expose the dummy gate electrodes, removing the exposed dummy gate electrodes to form trenches, and forming metal gate electrodes in the trenches.

摘要翻译： 一种方法包括在衬底上形成多个虚拟栅极结构，每个虚拟栅极结构包括伪栅极电极和伪栅极掩模，在衬底上形成第一绝缘层和虚拟栅极结构以填充虚拟栅极结构之间的第一空间 栅极结构，平坦化第一绝缘层和伪栅极结构的上部，去除剩余的第一绝缘层以暴露衬底的一部分，在剩余的虚设栅极结构和衬底的暴露部分上形成蚀刻停止层， 在所述蚀刻停止层上形成第二绝缘层以填充所述虚拟栅极结构之间的第二空间，平坦化所述第二绝缘层的上部和所述蚀刻停止层以暴露所述伪栅电极，去除所述暴露的伪栅电极以形成沟槽 并且在沟槽中形成金属栅电极。

公开(公告)号：US20120122283A1

公开(公告)日：2012-05-17

申请号：US13240560

申请日：2011-09-22

申请人： Jong-Won LEE ,  Jae-Seok Kim ,  Bo-Un Yoon

发明人： Jong-Won LEE ,  Jae-Seok Kim ,  Bo-Un Yoon

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L21/823842 ,  H01L21/823437 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7835

摘要： A method includes forming a plurality of dummy gate structures on a substrate, each dummy gate structure including a dummy gate electrode and a dummy gate mask, forming a first insulation layer on the substrate and the dummy gate structures to fill a first space between the dummy gate structures, planarizing upper portions of the first insulation layer and the dummy gate structures, removing the remaining first insulation layer to expose a portion of the substrate, forming an etch stop layer on the remaining dummy gate structures and the exposed portion of the substrate, forming a second insulation layer on the etch stop layer to fill a second space between the dummy gate structures, planarizing upper portions of the second insulation layer and the etch stop layer to expose the dummy gate electrodes, removing the exposed dummy gate electrodes to form trenches, and forming metal gate electrodes in the trenches.

摘要翻译： 一种方法包括在衬底上形成多个虚拟栅极结构，每个虚拟栅极结构包括伪栅极电极和伪栅极掩模，在衬底上形成第一绝缘层和虚拟栅极结构以填充虚拟栅极结构之间的第一空间 栅极结构，平坦化第一绝缘层和伪栅极结构的上部，去除剩余的第一绝缘层以暴露衬底的一部分，在剩余的虚设栅极结构和衬底的暴露部分上形成蚀刻停止层， 在所述蚀刻停止层上形成第二绝缘层以填充所述虚拟栅极结构之间的第二空间，平坦化所述第二绝缘层的上部和所述蚀刻停止层以暴露所述伪栅电极，去除所述暴露的伪栅电极以形成沟槽 并且在沟槽中形成金属栅电极。