公开(公告)号：US20050253218A1

公开(公告)日：2005-11-17

申请号：US11114693

申请日：2005-04-26

申请人： Chang-ki Jeon ,  Sung-Iyong Kim ,  Tae-hun Kwon

发明人： Chang-ki Jeon ,  Sung-Iyong Kim ,  Tae-hun Kwon

IPC分类号： H01L21/335 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/7816 ,  H01L27/0629 ,  H01L29/0615 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/7823

摘要： There is provided a high voltage gate driver integrated circuit. The high voltage gate driver integrated circuit includes: a high voltage region; a junction termination region surrounding the high voltage region; a low voltage region surrounding the junction termination region; a level shift transistor disposed between the high voltage region and the low voltage region, at least some portions of the level shift transistor being overlapped with the junction termination region; and/or a high voltage junction capacitor disposed between the high voltage region and the low voltage region, at least some portions of the high voltage junction capacitor being overlapped with the junction termination region.

摘要翻译： 提供了高压栅极驱动器集成电路。 高压栅极驱动器集成电路包括：高电压区域; 围绕高电压区域的接合端接区域; 围绕所述连接端接区域的低电压区域; 设置在所述高电压区域和所述低电压区域之间的电平移位晶体管，所述电平移位晶体管的至少一些部分与所述连接终止区域重叠; 和/或设置在高电压区域和低电压区域之间的高压结电容器，高压结电容器的至少一些部分与接合端接区域重叠。

公开(公告)号：US07655979B2

公开(公告)日：2010-02-02

申请号：US11950959

申请日：2007-12-05

申请人： Chang-Ki Jeon ,  Sung-Iyong Kim ,  Tae-hun Kwon

发明人： Chang-Ki Jeon ,  Sung-Iyong Kim ,  Tae-hun Kwon

IPC分类号： H01L29/772 ,  H01L21/265

CPC分类号： H01L29/7816 ,  H01L27/0629 ,  H01L29/0615 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/7823

摘要： There is provided a high voltage gate driver integrated circuit. The high voltage gate driver integrated circuit includes: a high voltage region; a junction termination region surrounding the high voltage region; a low voltage region surrounding the junction termination region; a level shift transistor disposed between the high voltage region and the low voltage region, at least some portions of the level shift transistor being overlapped with the junction termination region; and/or a high voltage junction capacitor disposed between the high voltage region and the low voltage region, at least some portions of the high voltage junction capacitor being overlapped with the junction termination region.

摘要翻译： 提供了高压栅极驱动器集成电路。 高压栅极驱动器集成电路包括：高电压区域; 围绕高电压区域的接合端接区域; 围绕所述连接端接区域的低电压区域; 设置在所述高电压区域和所述低电压区域之间的电平移位晶体管，所述电平移位晶体管的至少一些部分与所述连接终止区域重叠; 和/或设置在高电压区域和低电压区域之间的高压结电容器，高压结电容器的至少一些部分与接合端接区域重叠。

公开(公告)号：US07309894B2

公开(公告)日：2007-12-18

申请号：US11114693

申请日：2005-04-26

申请人： Chang-ki Jeon ,  Sung-lyong Kim ,  Tae-hun Kwon

发明人： Chang-ki Jeon ,  Sung-lyong Kim ,  Tae-hun Kwon

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L29/7816 ,  H01L27/0629 ,  H01L29/0615 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/7823

摘要： There is provided a high voltage gate driver integrated circuit. The high voltage gate driver integrated circuit includes: a high voltage region; a junction termination region surrounding the high voltage region; a low voltage region surrounding the junction termination region; a level shift transistor disposed between the high voltage region and the low voltage region, at least some portions of the level shift transistor being overlapped with the junction termination region; and/or a high voltage junction capacitor disposed between the high voltage region and the low voltage region, at least some portions of the high voltage junction capacitor being overlapped with the junction termination region.

摘要翻译： 提供了高压栅极驱动器集成电路。 高压栅极驱动器集成电路包括：高电压区域; 围绕高电压区域的接合端接区域; 围绕所述连接端接区域的低电压区域; 设置在所述高电压区域和所述低电压区域之间的电平移位晶体管，所述电平移位晶体管的至少一些部分与所述连接终止区域重叠; 和/或设置在高电压区域和低电压区域之间的高压结电容器，高压结电容器的至少一些部分与接合端接区域重叠。

公开(公告)号：US06933560B2

公开(公告)日：2005-08-23

申请号：US10661952

申请日：2003-09-12

申请人： Suk-kyun Lee ,  Cheol-joong Kim ,  Tae-hun Kwon

发明人： Suk-kyun Lee ,  Cheol-joong Kim ,  Tae-hun Kwon

IPC分类号： H01L21/336 ,  H01L23/58 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/72 ,  H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/0634 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66689

摘要： Power devices in which a low on-resistance can be obtained while maintaining a high breakdown voltage and a method for manufacturing the power devices are described. The power device includes a semiconductor substrate having a first conductivity type, a burying layer having a high concentration of a second conductivity type arranged deep in the semiconductor substrate, a well having a low concentration of a second conductivity type formed on the burying layer of the semiconductor substrate, a body region having a first conductivity type formed in a predetermined portion in the well having a low concentration of a second conductivity type, first and second channel stop regions having a low concentration of a second conductivity type, the first and second channel stop regions are formed in a predetermined portion of the body region and on both edges of the body region having a first conductivity type, a gate electrode including a gate insulating layer, formed on a space between the first and second channel stop regions, source and drain regions having a high concentration of a second conductivity type formed in the first and second channel stop regions on both sides of the gate electrode, and a body contact region formed in the source region. Only the body region having a first conductivity type exists between the first and second channel stop regions, and a channel is formed between the first and second channel stop regions.

摘要翻译： 描述能够在保持高击穿电压的同时获得低导通电阻的功率器件和用于制造功率器件的方法。 功率器件包括具有第一导电类型的半导体衬底，具有布置在半导体衬底中深度的第二导电类型的高浓度的掩埋层，形成在第二导电类型的埋藏层中的低浓度的第二导电类型的阱 半导体衬底，具有第一导电类型的体区，形成在具有低浓度的第二导电类型的阱中的预定部分中，具有低浓度的第二导电类型的第一和第二沟道停止区，第一和第二沟道 停止区域形成在身体区域的预定部分中，并且在具有第一导电类型的主体区域的两个边缘上，形成在第一和第二通道停止区域之间的空间上的栅极绝缘层，源极和 具有在第一和第二通道停止区域中形成的具有高浓度的第二导电类型的漏极区域 ns，并且形成在源极区域中的体接触区域。 在第一和第二通道停止区域之间仅存在具有第一导电类型的主体区域，并且在第一和第二通道停止区域之间形成通道。

公开(公告)号：US07888226B2

公开(公告)日：2011-02-15

申请号：US12229019

申请日：2008-08-18

申请人： Tae-hun Kwon ,  Cheol-joong Kim ,  Young-sub Jeong

发明人： Tae-hun Kwon ,  Cheol-joong Kim ,  Young-sub Jeong

IPC分类号： H01L21/331

CPC分类号： H01L29/7816 ,  H01L21/743 ,  H01L21/761 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/7823

摘要： A power semiconductor device has a first region in which a transistor is formed, a third region in which a control element is formed, and a second region for separating the first region and the third region. The power semiconductor device includes a substrate of a first conductive type and a semiconductor region of a second conductive type arranged on the substrate, and a highly-doped buried layer of the second conductive type and a highly-doped bottom layer of the first conductive type are arranged between the substrate and the semiconductor region, and the first highly-doped bottom layer of the first conductive type is arranged on a top side and a bottom side of the highly-doped buried layer in the first region and extends by a predetermined distance to the second region, and a first isolation region is arranged on the highly-doped bottom layer extending from the first region in the second region, and a highly-doped region of the second conductive type is arranged on the highly-doped buried layer, and a second isolation region is arranged on a second highly-doped bottom layer of the first conductive type . By such structure, parasitic bipolar junction transistors in the first isolation region and the second isolation region can be electrically separated from the third region.

摘要翻译： 功率半导体器件具有其中形成晶体管的第一区域，形成有控制元件的第三区域和用于分离第一区域和第三区域的第二区域。 功率半导体器件包括布置在衬底上的第一导电类型的衬底和第二导电类型的半导体区域，以及第二导电类型的高掺杂掩埋层和第一导电类型的高掺杂底层 布置在所述基板和所述半导体区域之间，并且所述第一导电类型的所述第一高掺杂底层布置在所述第一区域中的所述高度掺杂的掩埋层的顶侧和底侧上并且延伸预定距离 并且第一隔离区域布置在从第二区域中的第一区域延伸的高度掺杂的底层上，并且第二导电类型的高掺杂区域布置在高掺杂掩埋层上， 并且第二隔离区域布置在第一导电类型的第二高掺杂底层上。 通过这样的结构，第一隔离区域和第二隔离区域中的寄生双极结型晶体管可以与第三区域电分离。

公开(公告)号：US20050263800A1

公开(公告)日：2005-12-01

申请号：US11123400

申请日：2005-05-06

申请人： Tae-hun Kwon ,  Cheol-joong Kim ,  Young-sub Jeong

发明人： Tae-hun Kwon ,  Cheol-joong Kim ,  Young-sub Jeong

IPC分类号： H01L21/74 ,  H01L21/761 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78 ,  H01L29/788

CPC分类号： H01L29/7816 ,  H01L21/743 ,  H01L21/761 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/7823

摘要： A power semiconductor device has a first region in which a transistor is formed, a third region in which a control element is formed, and a second region for separating the first region and the third region. The power semiconductor device includes a substrate of a first conductive type and a semiconductor region of a second conductive type arranged on the substrate, and a highly-doped buried layer of the second conductive type and a highly-doped bottom layer of the first conductive type are arranged between the substrate and the semiconductor region, and the first highly-doped bottom layer of the first conductive type is arranged on a top side and a bottom side of the highly-doped buried layer in the first region and extends by a predetermined distance to the second region, and a first isolation region is arranged on the highly-doped bottom layer extending from the first region in the second region, and a highly-doped region of the second conductive type is arranged on the highly-doped buried layer, and a second isolation region is arranged on a second highly-doped bottom layer of the first conductive type. By such structure, parasitic bipolar junction transistors in the first isolation region and the second isolation region can be electrically separated from the third region.

摘要翻译： 功率半导体器件具有其中形成晶体管的第一区域，形成有控制元件的第三区域和用于分离第一区域和第三区域的第二区域。 功率半导体器件包括布置在衬底上的第一导电类型的衬底和第二导电类型的半导体区域，以及第二导电类型的高掺杂掩埋层和第一导电类型的高掺杂底层 布置在所述基板和所述半导体区域之间，并且所述第一导电类型的所述第一高掺杂底层布置在所述第一区域中的所述高度掺杂的掩埋层的顶侧和底侧上并且延伸预定距离 并且第一隔离区域布置在从第二区域中的第一区域延伸的高度掺杂的底层上，并且第二导电类型的高掺杂区域布置在高掺杂掩埋层上， 并且第二隔离区域布置在第一导电类型的第二高掺杂底层上。 通过这样的结构，第一隔离区域和第二隔离区域中的寄生双极结型晶体管可以与第三区域电分离。

公开(公告)号：US07420260B2

公开(公告)日：2008-09-02

申请号：US11123400

申请日：2005-05-06

申请人： Tae-hun Kwon ,  Cheol-joong Kim ,  Young-sub Jeong

发明人： Tae-hun Kwon ,  Cheol-joong Kim ,  Young-sub Jeong

IPC分类号： H01L29/06

CPC分类号： H01L29/7816 ,  H01L21/743 ,  H01L21/761 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/7823

摘要： A power semiconductor device has a first region in which a transistor is formed, a third region in which a control element is formed, and a second region for separating the first region and the third region. The power semiconductor device includes a substrate of a first conductive type and a semiconductor region of a second conductive type arranged on the substrate, and a highly-doped buried layer of the second conductive type and a highly-doped bottom layer of the first conductive type are arranged between the substrate and the semiconductor region, and the first highly-doped bottom layer of the first conductive type is arranged on a top side and a bottom side of the highly-doped buried layer in the first region and extends by a predetermined distance to the second region, and a first isolation region is arranged on the highly-doped bottom layer extending from the first region in the second region, and a highly-doped region of the second conductive type is arranged on the highly-doped buried layer, and a second isolation region is arranged on a second highly-doped bottom layer of the first conductive type. By such structure, parasitic bipolar junction transistors in the first isolation region and the second isolation region can be electrically separated from the third region.

摘要翻译： 功率半导体器件具有其中形成晶体管的第一区域，形成有控制元件的第三区域和用于分离第一区域和第三区域的第二区域。 功率半导体器件包括布置在衬底上的第一导电类型的衬底和第二导电类型的半导体区域，以及第二导电类型的高掺杂掩埋层和第一导电类型的高掺杂底层 布置在所述基板和所述半导体区域之间，并且所述第一导电类型的所述第一高掺杂底层布置在所述第一区域中的所述高度掺杂的掩埋层的顶侧和底侧上并且延伸预定距离 并且第一隔离区域布置在从第二区域中的第一区域延伸的高度掺杂的底层上，并且第二导电类型的高掺杂区域布置在高掺杂掩埋层上， 并且第二隔离区域布置在第一导电类型的第二高掺杂底层上。 通过这样的结构，第一隔离区域和第二隔离区域中的寄生双极结型晶体管可以与第三区域电分离。

公开(公告)号：US20080318401A1

公开(公告)日：2008-12-25

申请号：US12229019

申请日：2008-08-18

申请人： Tae-hun Kwon ,  Cheol-joong Kim ,  Young-sub Jeong

发明人： Tae-hun Kwon ,  Cheol-joong Kim ,  Young-sub Jeong

IPC分类号： H01L21/425

CPC分类号： H01L29/7816 ,  H01L21/743 ,  H01L21/761 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/7823

摘要： A power semiconductor device has a first region in which a transistor is formed, a third region in which a control element is formed, and a second region for separating the first region and the third region. The power semiconductor device includes a substrate of a first conductive type and a semiconductor region of a second conductive type arranged on the substrate, and a highly-doped buried layer of the second conductive type and a highly-doped bottom layer of the first conductive type are arranged between the substrate and the semiconductor region, and the first highly-doped bottom layer of the first conductive type is arranged on a top side and a bottom side of the highly-doped buried layer in the first region and extends by a predetermined distance to the second region, and a first isolation region is arranged on the highly-doped bottom layer extending from the first region in the second region, and a highly-doped region of the second conductive type is arranged on the highly-doped buried layer, and a second isolation region is arranged on a second highly-doped bottom layer of the first conductive type . By such structure, parasitic bipolar junction transistors in the first isolation region and the second isolation region can be electrically separated from the third region.

摘要翻译： 功率半导体器件具有其中形成晶体管的第一区域，形成有控制元件的第三区域和用于分离第一区域和第三区域的第二区域。 功率半导体器件包括布置在衬底上的第一导电类型的衬底和第二导电类型的半导体区域，以及第二导电类型的高掺杂掩埋层和第一导电类型的高掺杂底层 布置在所述基板和所述半导体区域之间，并且所述第一导电类型的所述第一高掺杂底层布置在所述第一区域中的所述高度掺杂的掩埋层的顶侧和底侧上并且延伸预定距离 并且第一隔离区域布置在从第二区域中的第一区域延伸的高度掺杂的底层上，并且第二导电类型的高掺杂区域布置在高掺杂掩埋层上， 并且第二隔离区域布置在第一导电类型的第二高掺杂底层上。 通过这样的结构，第一隔离区域和第二隔离区域中的寄生双极结型晶体管可以与第三区域电分离。

公开(公告)号：US06979875B2

公开(公告)日：2005-12-27

申请号：US10447558

申请日：2003-05-28

申请人： Tae-hun Kwon ,  Choel-joong Kim ,  Suk-kyun Lee

发明人： Tae-hun Kwon ,  Choel-joong Kim ,  Suk-kyun Lee

IPC分类号： H01L21/336 ,  H01L23/58 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/66681 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/7816

摘要： A power device and a method for manufacturing the same are provided. The power device comprises a first conductive semiconductor substrate; a second conductive buried layer formed to a certain depth within the semiconductor substrate; a second conductive epitaxial layer formed on the conductive buried layer; a first conductive well formed within the conductive epitaxial layer; a second conductive well formed within the second conductive epitaxial layer, on both sides of the first conductive well; a second conductive drift region formed in predetermined portions on the first and the second conductive well; and a lateral double diffused MOS transistor formed in the second conductive drift region. The breakdown voltage of the power device is controlled according to a distance between the first conductive well and the second conductive buried layer.

摘要翻译： 提供了一种功率器件及其制造方法。 功率器件包括第一导电半导体衬底; 在半导体衬底内形成一定深度的第二导电掩埋层; 形成在所述导电掩埋层上的第二导电外延层; 形成在所述导电外延层内的第一导电阱; 在所述第二导电外延层内形成的第二导电阱，位于所述第一导电阱的两侧; 形成在所述第一和第二导电孔上的预定部分中的第二导电漂移区; 以及形成在第二导电漂移区域中的横向双扩散MOS晶体管。 功率器件的击穿电压根据第一导电阱和第二导电掩埋层之间的距离来控制。