公开(公告)号：US06259284B1

公开(公告)日：2001-07-10

申请号：US09470256

申请日：1999-12-22

申请人： Changku Hwang ,  Hiroyuki Mizuno ,  Masayuki Miyazaki

发明人： Changku Hwang ,  Hiroyuki Mizuno ,  Masayuki Miyazaki

IPC分类号： H03L700

CPC分类号： H03K17/284 ,  H03K17/223

摘要： A novel structure and method are taught for fully discharging a capacitor and thereby reducing the capacitance needed to achieve a desired RC time constant. The invention overcomes the previously encountered problem of using a large and area-inefficient capacitor. The invention allows for conservation of integrated circuit space and is cost effective.

摘要翻译： 教导了一种新颖的结构和方法来完全放电电容器，从而减少实现期望的RC时间常数所需的电容。 本发明克服了先前遇到的使用大面积低效电容器的问题。 本发明允许对集成电路空间的保护，并且是成本有效的。

公开(公告)号：US20130271181A1

公开(公告)日：2013-10-17

申请号：US13449018

申请日：2012-04-17

申请人： Hoki Kim ,  Changku Hwang ,  Jinuk Shin

发明人： Hoki Kim ,  Changku Hwang ,  Jinuk Shin

IPC分类号： H03K19/0175

CPC分类号： H03K19/017509 ,  G06F1/26

摘要： A system and method of shifting a data signal from a first voltage domain having a first logic level to a second voltage domain having a second logic level, the second logic level having a second logical high state greater than a first logical high state in the first logic level and a single power supply logic level shifter circuit having a single power supply source, an input node and an output node, the input node coupled to a sender circuit in the first voltage domain and the output node coupled to a receiver circuit in the second voltage domain, the single power supply source being coupled only to a single power grid in the second voltage domain.

摘要翻译： 一种将数据信号从具有第一逻辑电平的第一电压域移位到具有第二逻辑电平的第二电压域的系统和方法，所述第二逻辑电平具有大于第一逻辑高状态的第二逻辑高状态 逻辑电平和具有单个电源，输入节点和输出节点的单个电源逻辑电平移位器电路，所述输入节点耦合到所述第一电压域中的发送器电路，并且所述输出节点耦合到所述第一电压源中的接收器电路 第二电压域，单个电源仅耦合到第二电压域中的单个电网。

公开(公告)号：US06535070B2

公开(公告)日：2003-03-18

申请号：US09754382

申请日：2001-01-05

申请人： Changku Hwang ,  Masaru Kokubo

发明人： Changku Hwang ,  Masaru Kokubo

IPC分类号： H03B502

CPC分类号： H03K3/0315 ,  H03L7/0893 ,  H03L7/0896 ,  H03L7/0995 ,  H03L7/10 ,  H03L2207/06

摘要： The variable frequency oscillator is capable of operation at a low power supply voltage and oscillating at a high frequency. A phase locked loop and a clock synchronizer use the variable frequency oscillator and have a wide oscillation frequency range. The variable frequency oscillator has plural delay cells which are cascaded and the output of the final stage delay cell is fed back to the input of the first stage delay cell. Each of the delay cells includes a differential amplifier and a positive feedback circuit, connected with input and output terminals intersecting with each other. The feedback circuit has complementary amplifiers each having an input terminal formed by connecting together gates of a pMOS and an nMOS transistor and an output terminal formed by connecting together the drains thereof.

摘要翻译： 变频振荡器能够在低电源电压下工作，并以高频振荡。 锁相环和时钟同步器使用可变频率振荡器并具有宽的振荡频率范围。 可变频率振荡器具有级联的多个延迟单元，并且最后级延迟单元的输出反馈到第一级延迟单元的输入。 每个延迟单元包括差分放大器和正反馈电路，与彼此相交的输入和输出端子连接。 反馈电路具有互补放大器，每个互补放大器具有通过将pMOS和nMOS晶体管的栅极连接在一起形成的输入端子和通过将其漏极连接而形成的输出端子。

公开(公告)号：US08816720B2

公开(公告)日：2014-08-26

申请号：US13449018

申请日：2012-04-17

申请人： Hoki Kim ,  Changku Hwang ,  Jinuk Shin

发明人： Hoki Kim ,  Changku Hwang ,  Jinuk Shin

IPC分类号： H03K19/0175

CPC分类号： H03K19/017509 ,  G06F1/26

摘要： A system and method of shifting a data signal from a first voltage domain having a first logic level to a second voltage domain having a second logic level, the second logic level having a second logical high state greater than a first logical high state in the first logic level and a single power supply logic level shifter circuit having a single power supply source, an input node and an output node, the input node coupled to a sender circuit in the first voltage domain and the output node coupled to a receiver circuit in the second voltage domain, the single power supply source being coupled only to a single power grid in the second voltage domain.

摘要翻译： 一种将数据信号从具有第一逻辑电平的第一电压域移位到具有第二逻辑电平的第二电压域的系统和方法，所述第二逻辑电平具有大于第一逻辑高状态的第二逻辑高状态 逻辑电平和具有单个电源，输入节点和输出节点的单个电源逻辑电平移位器电路，所述输入节点耦合到所述第一电压域中的发送器电路，并且所述输出节点耦合到所述第一电压源中的接收器电路 第二电压域，单个电源仅耦合到第二电压域中的单个电网。

公开(公告)号：US20140062548A1

公开(公告)日：2014-03-06

申请号：US13604795

申请日：2012-09-06

申请人： Changku Hwang ,  Sebastian Turullols ,  Daisy Jian ,  Ali Vahidsafa

发明人： Changku Hwang ,  Sebastian Turullols ,  Daisy Jian ,  Ali Vahidsafa

IPC分类号： H03L7/00 ,  H03L7/06

CPC分类号： H03K5/135

摘要： Embodiments include systems and methods for asynchronous, glitch-free clock switching across a wide range of clock frequencies with minimal clock down time. Embodiments effectively provide two stages of synchronization across two independent clock domains. In a first synchronization stage, a received, asynchronous clock select signal is translated into a synchronized clock select signal that is effectively synchronous with respect to a first clock domain and is still effectively asynchronous with respect to a second clock domain. In a second synchronization stage, the synchronized clock select signal is resynchronized so as to be effectively synchronous with respect to the second clock domain. The synchronized select signal can be used to disable the clock of the first clock domain, and the resynchronized clock select signal can be used to enable the clock of the second clock domain.

摘要翻译： 实施例包括用于在具有最小时钟停机时间的宽范围的时钟频率上进行异步，无毛刺时钟切换的系统和方法。 实施例有效地提供跨两个独立时钟域的两个阶段的同步。 在第一同步阶段，接收到的异步时钟选择信号被转换成相对于第一时钟域有效同步的同步时钟选择信号，并且相对于第二时钟域仍然有效地是异步的。 在第二同步级中，同步的时钟选择信号被重新同步，以便相对于第二时钟域有效地同步。 同步选择信号可用于禁用第一时钟域的时钟，并且重新同步的时钟选择信号可用于启用第二时钟域的时钟。

公开(公告)号：US08729947B2

公开(公告)日：2014-05-20

申请号：US13604795

申请日：2012-09-06

申请人： Changku Hwang ,  Sebastian Turullols ,  Daisy Jian ,  Ali Vahidsafa

发明人： Changku Hwang ,  Sebastian Turullols ,  Daisy Jian ,  Ali Vahidsafa

IPC分类号： G06F1/04 ,  H03K3/00

CPC分类号： H03K5/135

摘要： Embodiments include systems and methods for asynchronous, glitch-free clock switching across a wide range of clock frequencies with minimal clock down time. Embodiments effectively provide two stages of synchronization across two independent clock domains. In a first synchronization stage, a received, asynchronous clock select signal is translated into a synchronized clock select signal that is effectively synchronous with respect to a first clock domain and is still effectively asynchronous with respect to a second clock domain. In a second synchronization stage, the synchronized clock select signal is resynchronized so as to be effectively synchronous with respect to the second clock domain. The synchronized select signal can be used to disable the clock of the first clock domain, and the resynchronized clock select signal can be used to enable the clock of the second clock domain.

摘要翻译： 实施例包括用于在具有最小时钟停机时间的宽范围的时钟频率上进行异步，无毛刺时钟切换的系统和方法。 实施例有效地提供跨两个独立时钟域的两个阶段的同步。 在第一同步阶段，接收到的异步时钟选择信号被转换成相对于第一时钟域有效同步的同步时钟选择信号，并且相对于第二时钟域仍然有效地是异步的。 在第二同步级中，同步的时钟选择信号被重新同步，以便相对于第二时钟域有效地同步。 同步选择信号可用于禁用第一时钟域的时钟，并且重新同步的时钟选择信号可用于启用第二时钟域的时钟。

公开(公告)号：US08604852B1

公开(公告)日：2013-12-10

申请号：US13610469

申请日：2012-09-11

申请人： Sebastian Turullols ,  Changku Hwang ,  Daniel Woo ,  Yifan YangGong

发明人： Sebastian Turullols ,  Changku Hwang ,  Daniel Woo ,  Yifan YangGong

IPC分类号： H03L7/06

CPC分类号： H03L7/099 ,  H03L7/07 ,  H03L7/23

摘要： In an integrated circuit that provides a clock signal, an asymmetric frequency-locked loop (AFLL) includes a first digitally controlled oscillator (DCO) that outputs a first signal having a first fundamental frequency, and a second DCO that outputs a second signal having a second fundamental frequency that is less than the first fundamental frequency. Moreover, the AFLL includes control logic that selects one of the first DCO and the second DCO based on an instantaneous value of a power-supply voltage and an average power-supply voltage so that an impact of power-supply voltage variations on a time-critical path in the integrated circuit is reduced. For example, the control logic may select the first DCO if the instantaneous value of the power-supply voltage is greater than the average power-supply voltage; otherwise, the control logic may select the second DCO.

摘要翻译： 在提供时钟信号的集成电路中，非对称频率锁相环（AFLL）包括输出具有第一基频的第一信号的第一数字控制振荡器（DCO）和输出具有第一基频的第二信号的第二DCO， 第二基频小于第一基频。 此外，AFLL包括基于电源电压和平均电源电压的瞬时值来选择第一DCO和第二DCO中的一个的控制逻辑，使得电源电压的变化对时间 - 集成电路中的关键路径减少。 例如，如果电源电压的瞬时值大于平均电源电压，则控制逻辑可以选择第一DCO; 否则，控制逻辑可以选择第二DCO。

公开(公告)号：US06215364B1

公开(公告)日：2001-04-10

申请号：US09288689

申请日：1999-04-09

申请人： Changku Hwang ,  Masaru Kokubo

发明人： Changku Hwang ,  Masaru Kokubo

IPC分类号： H03B502

CPC分类号： H03K3/0315 ,  H03L7/0893 ,  H03L7/0896 ,  H03L7/0995 ,  H03L7/10 ,  H03L2207/06

摘要： The variable frequency oscillator is capable of operation at a low power supply voltage and oscillating at a high frequency. A phase locked loop and a clock synchronizer use the variable frequency oscillator and have a wide oscillation frequency range. The variable frequency oscillator has plural delay cells which are cascaded and the output of the final stage delay cell is fed back to the input of the first stage delay cell. Each of the delay cells includes a differential amplifier and a positive feedback circuit, connected with input and output terminals intersecting with each other. The feedback circuit has complementary amplifiers each having an input terminal formed by connecting together gates of a pMOS and an nMOS transistor and an output terminal formed by connecting together the drains thereof. The positive feedback circuit, provided between output terminals of the differential amplifier, a controlling MOS transistor for inputting a frequency control signal for controlling the source current of the complementary amplifier to the gate thereof and the complementary amplifiers are connected in series between a power supply terminal and a ground terminal.

摘要翻译： 变频振荡器能够在低电源电压下工作，并以高频振荡。 锁相环和时钟同步器使用可变频率振荡器并具有宽的振荡频率范围。 可变频率振荡器具有级联的多个延迟单元，并且最后级延迟单元的输出反馈到第一级延迟单元的输入。 每个延迟单元包括差分放大器和正反馈电路，与彼此相交的输入和输出端子连接。 反馈电路具有互补放大器，每个互补放大器具有通过将pMOS和nMOS晶体管的栅极连接在一起形成的输入端子和通过将其漏极连接而形成的输出端子。 在差分放大器的输出端子之间设置的正反馈电路，用于输入用于控制互补放大器的源电流至其栅极的频率控制信号的控制MOS晶体管和互补放大器串联连接在电源端子 和地面终端。