公开(公告)号：US20110063281A1

公开(公告)日：2011-03-17

申请号：US12603579

申请日：2009-10-21

申请人： Chao-Ching Hsu ,  Wei-Cheng Lin ,  Yu-Chun Tsai

发明人： Chao-Ching Hsu ,  Wei-Cheng Lin ,  Yu-Chun Tsai

IPC分类号： G09G5/00

CPC分类号： G09G3/3648 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2300/0465 ,  G09G2310/0297 ,  G09G2320/0223

摘要： A pixel array, a driving method thereof and a flat panel display using the same are provided. The pixel array includes a first, a second, a third, and a fourth scan lines. A plurality of pixels is disposed between the first and the second scan lines. A plurality of pixels is disposed between the third and the fourth scan lines. In a first frame period, a gate driving circuit sequentially provides a driving signal to the first, the second, the fourth and the third scan lines. In a second frame period, the gate driving circuit sequentially provides the driving signal to the second, the first, the third and the fourth scan lines.

摘要翻译： 提供像素阵列，其驱动方法和使用其的平板显示器。 像素阵列包括第一，第二，第三和第四扫描线。 多个像素设置在第一和第二扫描线之间。 多个像素设置在第三和第四扫描线之间。 在第一帧周期中，栅极驱动电路依次向第一，第二，第四和第三扫描线提供驱动信号。 在第二帧周期中，栅极驱动电路依次向第二扫描线，第一扫描线，第三扫描线和第四扫描线提供驱动信号。

公开(公告)号：US08803854B2

公开(公告)日：2014-08-12

申请号：US12790994

申请日：2010-06-01

申请人： Ching-Lin Li ,  Yu-Chun Tsai ,  Chao-Ching Hsu ,  Shih-Yuan Su

发明人： Ching-Lin Li ,  Yu-Chun Tsai ,  Chao-Ching Hsu ,  Shih-Yuan Su

IPC分类号： G06F3/038

CPC分类号： G09G3/3677 ,  G09G3/20 ,  G09G3/3413 ,  G09G3/3611 ,  G09G3/3648 ,  G09G2310/0264 ,  G09G2310/0267 ,  G09G2310/027 ,  G09G2320/02 ,  G09G2320/0223 ,  G09G2320/0233

摘要： A gate driver and a liquid crystal display using the same are provided. The gate driver includes a scan signal generating unit and a compensation unit. The scan signal generating unit has a plurality of output channels, and is used for sequentially outputting a scan signal through the output channels according to a basic clock and a start pulse. The compensation unit is coupled to the scan signal generating unit, and used for compensating the total resistance of each of the output channels, and sequentially receiving and transmitting the scan signal to a display panel.

摘要翻译： 提供了栅极驱动器和使用其的液晶显示器。 栅极驱动器包括扫描信号产生单元和补偿单元。 扫描信号产生单元具有多个输出通道，并且用于根据基本时钟和起始脉冲通过输出通道依次输出扫描信号。 补偿单元耦合到扫描信号生成单元，用于补偿每个输出通道的总电阻，并且顺序地将扫描信号传送到显示面板。

公开(公告)号：US20110248977A1

公开(公告)日：2011-10-13

申请号：US12790994

申请日：2010-06-01

申请人： Ching-Lin Li ,  Yu-Chun Tsai ,  Chao-Ching Hsu ,  Shih-Yuan Su

发明人： Ching-Lin Li ,  Yu-Chun Tsai ,  Chao-Ching Hsu ,  Shih-Yuan Su

IPC分类号： G09G3/36 ,  G06F3/038

CPC分类号： G09G3/3677 ,  G09G3/20 ,  G09G3/3413 ,  G09G3/3611 ,  G09G3/3648 ,  G09G2310/0264 ,  G09G2310/0267 ,  G09G2310/027 ,  G09G2320/02 ,  G09G2320/0223 ,  G09G2320/0233

摘要： A gate driver and a liquid crystal display using the same are provided. The gate driver includes a scan signal generating unit and a compensation unit. The scan signal generating unit has a plurality of output channels, and is used for sequentially outputting a scan signal through the output channels according to a basic clock and a start pulse. The compensation unit is coupled to the scan signal generating unit, and used for compensating the total resistance of each of the output channels, and sequentially receiving and transmitting the scan signal to a display panel.

摘要翻译： 提供了栅极驱动器和使用其的液晶显示器。 栅极驱动器包括扫描信号产生单元和补偿单元。 扫描信号产生单元具有多个输出通道，并且用于根据基本时钟和起始脉冲通过输出通道依次输出扫描信号。 补偿单元耦合到扫描信号生成单元，用于补偿每个输出通道的总电阻，并且顺序地将扫描信号传送到显示面板。

公开(公告)号：US20090009462A1

公开(公告)日：2009-01-08

申请号：US11853026

申请日：2007-09-11

申请人： Chao-Ching Hsu ,  Cheng-Liang Ma ,  Wei-cheng Lin

发明人： Chao-Ching Hsu ,  Cheng-Liang Ma ,  Wei-cheng Lin

IPC分类号： G09G3/36

CPC分类号： G02F1/133305 ,  G02F1/1345 ,  G09G3/3611 ,  G09G3/3666 ,  G09G2300/0426 ,  G09G2310/0281 ,  G09G2330/021

摘要： An LCD panel including a liquid crystal cell array, gate driving integrated circuits (ICs), first source driving ICs, second source driving ICs and a timing control circuit is provided. The liquid crystal cell array has a first display area and a second display area. The first and the second source driving ICs are electrically connected with the first and the second display areas, respectively, while the timing control circuit is electrically connected with the source and the gate driving ICs. The LCD panel is driven by writing data into the first display area through the first source driving ICs via a first receiving/transmitting mode and writing data into the second display area through the second source driving ICs via a second receiving/transmitting mode. The first data receiving/transmitting mode is different from the second receiving/transmitting mode.

摘要翻译： 提供了包括液晶单元阵列的LCD面板，栅极驱动集成电路（IC），第一源极驱动IC，第二源极驱动IC和定时控制电路。 液晶单元阵列具有第一显示区域和第二显示区域。 第一和第二源极驱动IC分别与第一和第二显示区域电连接，同时定时控制电路与源极和栅极驱动IC电连接。 通过第一接收/发送模式通过第一源极驱动IC将数据写入第一显示区域并通过第二接收/发送模式通过第二源极驱动IC将数据写入第二显示区域来驱动LCD面板。 第一数据接收/发送模式与第二接收/发送模式不同。

公开(公告)号：US08982030B2

公开(公告)日：2015-03-17

申请号：US12837103

申请日：2010-07-15

申请人： Kai-Yuan Siao ,  Jian-Feng Li ,  Hsiao-Chung Cheng ,  Tsung-Hung Lee ,  Chao-Ching Hsu

发明人： Kai-Yuan Siao ,  Jian-Feng Li ,  Hsiao-Chung Cheng ,  Tsung-Hung Lee ,  Chao-Ching Hsu

IPC分类号： G09G3/36 ,  G09G3/20

CPC分类号： G09G3/20 ,  G09G2310/0267

摘要： A gate output control method is adapted into a flat display having a plurality of gate drive integrated circuits. The method comprises: providing a gate control signal; providing a oblique control signal to oblique modulate the gate control signal for generating a gate control signal with oblique; modulating the gate control signal with oblique to obtain a modulated gate control signal; and outputting the modulated gate control signal to the gate drive integrated circuits. A falling edge of the modulated gate control signal comprises a oblique-varying period and a vertical-varying period. In the oblique-varying period, the modulated gate control signal firstly changes to a predetermined voltage in a first slope, and then changes in a second slope until the vertical-varying period. In the vertical-varying period, the modulated gate control signal changes vertically or nearly vertically.

摘要翻译： 栅极输出控制方法适用于具有多个栅极驱动集成电路的平面显示器。 该方法包括：提供门控制信号; 提供倾斜控制信号以倾斜调制用于产生具有倾斜的栅极控制信号的栅极控制信号; 调制栅极控制信号以获得调制的栅极控制信号; 并将调制的栅极控制信号输出到栅极驱动集成电路。 调制的栅极控制信号的下降沿包括倾斜变化周期和垂直变化周期。 在倾斜变化期间，调制后的栅极控制信号首先以第一斜率变化为预定电压，然后以第二斜率变化，直到垂直变化周期为止。 在垂直变化期间，调制栅极控制信号垂直或几乎垂直地变化。

公开(公告)号：US08605022B2

公开(公告)日：2013-12-10

申请号：US13275419

申请日：2011-10-18

申请人： Jen-Chieh Chen ,  Chao-Ching Hsu ,  Tzu-Hui Hsu

发明人： Jen-Chieh Chen ,  Chao-Ching Hsu ,  Tzu-Hui Hsu

IPC分类号： G09G5/02

CPC分类号： G09G3/3614 ,  G09G3/2044

摘要： An exemplary image displaying method for a display device includes steps of: providing display data to pixels of the display device for displaying images; taking a special amount of frame of images as an image group, making polarities of a same pixel being of adjacent two frame of images in the image group and using a same polarity inversion in the adjacent two frame of images be different from each other, and making polarities of a same pixel being of the last frame of image in a former one of adjacent two image groups and of the first frame of image in a latter one of the adjacent two image groups and using the same polarity inversion in the last and first frame of images be the same with each other.

公开(公告)号：US08436801B2

公开(公告)日：2013-05-07

申请号：US12684908

申请日：2010-01-09

申请人： Chao-Ching Hsu ,  Mu-Lin Tung ,  Chung-Shen Cheng

发明人： Chao-Ching Hsu ,  Mu-Lin Tung ,  Chung-Shen Cheng

IPC分类号： G09G3/36

CPC分类号： H03K19/0175 ,  G09G3/3677 ,  G09G2310/0289 ,  G09G2330/023

摘要： A level shift circuit includes a control logic circuit, a plurality of level shift output buffers and a plurality of charge sharing circuits. The control logic circuit receives input clock pulse signals and a charge sharing signal and acquires voltage level information of each received signal. Each output buffer amplifies a corresponding input clock pulse signal and determines whether to output a signal according to the acquired information of the charge sharing signal. Each charge sharing circuit determines whether to be turned on according to the acquired information of a corresponding input clock pulse signal. When a charge sharing circuit is turned on, the output terminal of a corresponding output buffer and a predetermined voltage level are coupled to each other by the charge sharing circuit, so as to perform the charge sharing operation. Furthermore, a corresponding liquid crystal display device and a corresponding charge sharing method are also provided.

摘要翻译： 电平移位电路包括控制逻辑电路，多个电平移位输出缓冲器和多个电荷共享电路。 控制逻辑电路接收输入时钟脉冲信号和电荷共享信号，并获取每个接收信号的电压电平信息。 每个输出缓冲器放大对应的输入时钟脉冲信号，并根据获取的电荷共享信号的信息确定是否输出信号。 每个电荷共享电路根据所获取的相应输入时钟脉冲信号的信息确定是否被接通。 当电荷共享电路接通时，相应的输出缓冲器的输出端和预定的电压电平通过电荷共享电路彼此耦合，从而进行电荷共享操作。 此外，还提供了相应的液晶显示装置和相应的电荷共享方法。

公开(公告)号：US09105247B2

公开(公告)日：2015-08-11

申请号：US12848717

申请日：2010-08-02

申请人： Yi-Fan Lin ,  Mu-Lin Tung ,  Chao-Ching Hsu

发明人： Yi-Fan Lin ,  Mu-Lin Tung ,  Chao-Ching Hsu

IPC分类号： G06F3/038 ,  G09G3/36

CPC分类号： G09G3/3614 ,  G09G2300/0426 ,  G09G2330/021

摘要： A display device includes multiple first data lines, multiple second data lines, multiple pixel columns, at least a first charge sharing switch circuit and at least a second charge sharing switch circuit. The second data lines are alternately arranged with the first data lines. Each of the pixel columns includes multiple first pixels and multiple second pixels. The first pixels of each of the pixel columns are coupled to one of the first data lines, and the second pixels of each of the pixel columns are coupled to one of the second data lines. The first charge sharing switch circuit each is electrically coupled to at least a part of the first data lines. The second charge sharing switch circuit each is electrically coupled to at least a part of the second data lines. A display device driving method and a source driving circuit also are provided.

摘要翻译： 显示装置包括多个第一数据线，多个第二数据线，多个像素列，至少第一电荷共享开关电路和至少第二电荷共享开关电路。 第二数据线与第一数据线交替布置。 每个像素列包括多个第一像素和多个第二像素。 每个像素列的第一像素被耦合到第一数据线中的一个，并且每个像素列的第二像素被耦合到第二数据线之一。 第一电荷共享开关电路各自电耦合到第一数据线的至少一部分。 第二电荷共享开关电路各自电耦合到第二数据线的至少一部分。 还提供了一种显示装置驱动方法和源极驱动电路。

公开(公告)号：US08605067B2

公开(公告)日：2013-12-10

申请号：US13308815

申请日：2011-12-01

申请人： Jen-Chieh Chen ,  Chao-Ching Hsu ,  Ching-Lin Li

发明人： Jen-Chieh Chen ,  Chao-Ching Hsu ,  Ching-Lin Li

IPC分类号： G06F3/038 ,  G09G5/00

CPC分类号： G09G3/3614 ,  G09G3/3688 ,  G09G2310/0224 ,  G09G2310/0248 ,  G09G2310/0275 ,  G09G2310/0297 ,  G09G2330/023

摘要： A source-driving circuit comprises a plurality of first and second data-outputting units, a first and a second charge-sharing units and a charge-sharing switch circuit. The first and second data-outputting units have corresponding first and second output terminals respectively for outputting data signals with a first polarity and a second polarity. The first and second charge-sharing units comprise a plurality of first and second switches respectively. Each first switch is electrically connected between each two first output terminals and each two second output terminals. Each second switch is electrically connected between one of the first outputting terminals and a corresponding one of the second outputting terminals. A charge-sharing switch circuit is electrically connected to the first and second charge-sharing units for outputting a switch signal to the first and second charge-sharing units according to a polarity signal, so as to determine the on/off statuses of the first and second switches.

摘要翻译： 源极驱动电路包括多个第一和第二数据输出单元，第一和第二电荷共享单元和电荷共享开关电路。 第一和第二数据输出单元分别具有相应的第一和第二输出端，用于输出具有第一极性和第二极性的数据信号。 第一和第二电荷共享单元分别包括多个第一和第二开关。 每个第一开关电连接在每两个第一输出端子和每两个第二输出端子之间。 每个第二开关电连接在第一输出端子之一和第二输出端子中的相应一个之间。 电荷共享开关电路电连接到第一和第二电荷共享单元，用于根据极性信号将开关信号输出到第一和第二电荷共享单元，以便确定第一和第二电荷共享单元的开/关状态 和第二开关。

公开(公告)号：US08542226B2

公开(公告)日：2013-09-24

申请号：US13112573

申请日：2011-05-20

申请人： Jian-Feng Li ,  Chao-Ching Hsu ,  Jen-Chieh Chen

发明人： Jian-Feng Li ,  Chao-Ching Hsu ,  Jen-Chieh Chen

IPC分类号： G06F3/038

CPC分类号： G09G3/3696 ,  G09G3/3677 ,  G09G2310/066 ,  G09G2310/08 ,  G09G2320/0219

摘要： A gate pulse modulating circuit includes a timing controller capable of generating an output enable signal and a plurality of timing control signals; a high gate voltage generating unit, electrically connected to the timing controller for receiving the timing control signals, capable of generating a high gate voltage with a waveform including a plurality of cutting edges in response to the timing control signals; a low gate voltage generating unit capable of generating a low gate voltage; and a gate driver, electrically connected to the timing controller for receiving the output enable signal and the high gate voltage generating unit for receiving the high gate voltage and the low gate voltage generating unit for receiving the low gate voltage, capable of generating a plurality of gate pulses in response to a plurality of enable periods of the output enable signal; wherein a waveform of the gate pulses includes a plurality of cutting edges.

摘要翻译： 门脉冲调制电路包括能够产生输出使能信号和多个定时控制信号的定时控制器; 高门电压产生单元，电连接到用于接收定时控制信号的定时控制器，能够响应于定时控制信号，产生具有包括多个切削刃的波形的高栅极电压; 能够产生低栅极电压的低栅极电压产生单元; 以及栅极驱动器，电连接到用于接收输出使能信号的定时控制器和用于接收高栅极电压的高栅极电压产生单元和用于接收低栅极电压的低栅极电压产生单元，其能够产生多个 响应于所述输出使能信号的多个使能周期; 其中所述栅极脉冲的波形包括多个切割边缘。