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公开(公告)号：US08788867B2
公开(公告)日：2014-07-22
申请号：US12930461
申请日：2011-01-07
CPC分类号： H04L65/80 , G06F1/025 , G06F1/0321
摘要： Systems and methods are disclosed for playback of detected timing events with detected phase variations. Disclosed signal generation embodiments can be used to generate digital signals having desired phase variation. Disclosed event detection circuitry can be used to generate event timing data representing one or more phase variations in detected events. The disclosed signal generation embodiments can utilize the event timing data to playback detect events along with the measured phase variations. Further, the signal generation circuitry and the event detection circuitry can be implemented in different devices or can be implemented in the same device.
摘要翻译： 公开了用于回放检测到的相位变化的定时事件的系统和方法。 公开的信号生成实施例可用于产生具有所需相位变化的数字信号。 公开的事件检测电路可以用于产生表示检测到的事件中的一个或多个相位变化的事件定时数据。 所公开的信号发生实施例可以利用事件定时数据与测量的相位变化一起重放检测事件。 此外，信号产生电路和事件检测电路可以在不同的设备中实现，或者可以在相同的设备中实现。
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公开(公告)号：US08683254B2
公开(公告)日：2014-03-25
申请号：US12930491
申请日：2011-01-07
IPC分类号： G06F1/00
CPC分类号： G04F10/00
摘要： Systems and methods are disclosed for precise event time measurement. High speed serializer and deserializer circuitry are combined with high speed logic elements, such as exclusive-OR (XOR) or exclusive-not-OR (XNOR) logic circuitry, to achieve a measurement precision based upon a bit period associated with the high speed circuitry rather than upon slower reference clock signals. In certain embodiments, the disclosed systems and methods generate digital signal patterns, serialize them, transmit them as a high speed bit stream, utilize an event occurrence signal and logic circuitry to produce a modified bit stream, deserialize the modified bit stream to produce a modified digital signal pattern, compare the modified signal pattern with a predicted signal pattern, and determine bit positions or bit periods at which events occur based upon this comparison. These bit positions can then be used to generate precise timestamps and related time information for detected events.
摘要翻译： 公开了用于精确事件时间测量的系统和方法。 高速串行器和解串器电路与诸如异或（XOR）或异或非（XNOR）逻辑电路的高速逻辑元件组合，以基于与高速电路相关联的位周期来实现测量精度 而不是较慢的参考时钟信号。 在某些实施例中，所公开的系统和方法产生数字信号模式，将它们串行化，将其作为高速比特流传输，利用事件发生信号和逻辑电路产生经修改的比特流，对修改的比特流进行反序列化以产生修改的 数字信号模式，将修改的信号模式与预测信号模式进行比较，并且基于该比较来确定事件发生的位位置或位周期。 然后可以使用这些位位置来为检测到的事件产生精确的时间戳和相关的时间信息。
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3.发明授权Systems and methods for precise timing measurements using high-speed deserializers 有权使用高速解串器进行精确定时测量的系统和方法公开(公告)号：US08533518B2
公开(公告)日：2013-09-10
申请号：US12930495
申请日：2011-01-07
IPC分类号： G06F1/00
CPC分类号： G01R31/31725 , G01R31/31716
摘要： Systems and methods are disclosed for precise event time measurement using high-speed deserializer circuitry. The described embodiments utilize high speed deserializer circuitry to achieve a precision based upon a bit period associated with the operation of the high speed operation of the deserializer circuitry rather than upon slower speed clock periods associated with reference clock signals. In certain embodiments, the disclosed systems and methods receive an event occurrence signal and use deserializer circuitry to sample the event occurrence signal and to produce multi-bit parallel data representing the event occurrence signal. Precise timestamps can then be generated based upon the multi-bit parallel data. Advantageously, the precision of these time measurements is associated with the bit period of the high speed operation of the deserializer circuitry and are not limited to lower speeds at which other circuitry within the system may be operating, for example, based upon a slower reference clock signal.
摘要翻译： 公开了使用高速解串器电路的精确事件时间测量的系统和方法。 所描述的实施例利用高速解串器电路来实现基于与解串行器电路的高速操作的操作相关联的位周期的精度，而不是与参考时钟信号相关联的较慢速度的时钟周期。 在某些实施例中，所公开的系统和方法接收事件发生信号，并使用解串器电路对事件发生信号进行采样并产生表示事件发生信号的多位并行数据。 然后可以基于多位并行数据来产生精确的时间戳。 有利地，这些时间测量的精度与解串行器电路的高速操作的位周期相关联，并且不限于例如基于较慢的参考时钟的系统内的其它电路可以操作的较低速度 信号。
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4.发明申请Systems and methods for precise timing measurements using high-speed deserializers 有权使用高速解串器进行精确定时测量的系统和方法公开(公告)号：US20120179422A1
公开(公告)日：2012-07-12
申请号：US12930495
申请日：2011-01-07
IPC分类号： G06F17/40
CPC分类号： G01R31/31725 , G01R31/31716
摘要： Systems and methods are disclosed for precise event time measurement using high-speed deserializer circuitry. The described embodiments utilize high speed deserializer circuitry to achieve a precision based upon a bit period associated with the operation of the high speed operation of the deserializer circuitry rather than upon slower speed clock periods associated with reference clock signals. In certain embodiments, the disclosed systems and methods receive an event occurrence signal and use deserializer circuitry to sample the event occurrence signal and to produce multi-bit parallel data representing the event occurrence signal. Precise timestamps can then be generated based upon the multi-bit parallel data. Advantageously, the precision of these time measurements is associated with the bit period of the high speed operation of the deserializer circuitry and are not limited to lower speeds at which other circuitry within the system may be operating, for example, based upon a slower reference clock signal.
摘要翻译： 公开了使用高速解串器电路的精确事件时间测量的系统和方法。 所描述的实施例利用高速解串器电路来实现基于与解串行器电路的高速操作的操作相关联的位周期的精度，而不是与参考时钟信号相关联的较慢速度的时钟周期。 在某些实施例中，所公开的系统和方法接收事件发生信号，并使用解串器电路对事件发生信号进行采样并产生表示事件发生信号的多位并行数据。 然后可以基于多位并行数据来产生精确的时间戳。 有利地，这些时间测量的精度与解串行器电路的高速操作的位周期相关联，并且不限于例如基于更慢的参考时钟的系统内的其它电路可以工作的较低速度 信号。
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公开(公告)号：US20120176172A1
公开(公告)日：2012-07-12
申请号：US12930461
申请日：2011-01-07
IPC分类号： H03K3/84
CPC分类号： H04L65/80 , G06F1/025 , G06F1/0321
摘要： Systems and methods are disclosed for playback of detected timing events with detected phase variations. Disclosed signal generation embodiments can be used to generate digital signals having desired phase variation. Disclosed event detection circuitry can be used to generate event timing data representing one or more phase variations in detected events. The disclosed signal generation embodiments can utilize the event timing data to playback detect events along with the measured phase variations. Further, the signal generation circuitry and the event detection circuitry can be implemented in different devices or can be implemented in the same device.
摘要翻译： 公开了用于回放检测到的相位变化的定时事件的系统和方法。 公开的信号生成实施例可用于产生具有所需相位变化的数字信号。 公开的事件检测电路可以用于产生表示检测到的事件中的一个或多个相位变化的事件定时数据。 所公开的信号发生实施例可以利用事件定时数据与测量的相位变化一起重放检测事件。 此外，信号产生电路和事件检测电路可以在不同的设备中实现，或者可以在相同的设备中实现。
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公开(公告)号：US20120176159A1
公开(公告)日：2012-07-12
申请号：US12930491
申请日：2011-01-07
IPC分类号： H03K5/19
CPC分类号： G04F10/00
摘要： Systems and methods are disclosed for precise event time measurement. High speed serializer and deserializer circuitry are combined with high speed logic elements, such as exclusive-OR (XOR) or exclusive-not-OR (XNOR) logic circuitry, to achieve a measurement precision based upon a bit period associated with the high speed circuitry rather than upon slower reference clock signals. In certain embodiments, the disclosed systems and methods generate digital signal patterns, serialize them, transmit them as a high speed bit stream, utilize an event occurrence signal and logic circuitry to produce a modified bit stream, deserialize the modified bit stream to produce a modified digital signal pattern, compare the modified signal pattern with a predicted signal pattern, and determine bit positions or bit periods at which events occur based upon this comparison. These bit positions can then be used to generate precise timestamps and related time information for detected events.
摘要翻译： 公开了用于精确事件时间测量的系统和方法。 高速串行器和解串器电路与诸如异或（XOR）或异或非（XNOR）逻辑电路的高速逻辑元件组合，以基于与高速电路相关联的位周期来实现测量精度 而不是较慢的参考时钟信号。 在某些实施例中，所公开的系统和方法产生数字信号模式，将它们串行化，将其作为高速比特流传输，利用事件发生信号和逻辑电路产生经修改的比特流，对修改的比特流进行反序列化以产生修改的 数字信号模式，将修改的信号模式与预测信号模式进行比较，并且基于该比较来确定事件发生的位位置或位周期。 然后可以使用这些位位置来为检测到的事件产生精确的时间戳和相关的时间信息。
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7.发明授权Filtering path view graphical user interfaces and related systems and methods 有权过滤路径视图图形用户界面及相关系统和方法公开(公告)号：US08934495B1
公开(公告)日：2015-01-13
申请号：US12462222
申请日：2009-07-31
申请人： Gregory S. Hilton , Ronald A. Pleshek , Charles A. Webb, III , Keith E. Cheney , Himanshu M. Thaker
发明人： Gregory S. Hilton , Ronald A. Pleshek , Charles A. Webb, III , Keith E. Cheney , Himanshu M. Thaker
CPC分类号： H04L67/02 , H04L41/22 , H04L43/028 , H04L43/12 , H04L65/1006 , H04L67/2828 , H04L67/322 , H04L67/36
摘要： Systems and methods are disclosed that allow for improved management and control of packet forwarding in network systems. Network devices and tool optimizers and a related systems and methods are disclosed for improved packet forwarding between network sources and destination tools in a network monitoring environment. The network devices and tool optimizers disclosed can include a graphical user interfaces (GUIs) through which a user can create and modify filters and select associated filter criteria for forwarding packets from input ports to output ports. The network devices and tool optimizers can also automatically generate filter rules and apply them to the appropriate filter engines so that packets are forwarded as desired by the user. The GUI can be configured to provide other features as well.
摘要翻译： 公开了允许改进网络系统中分组转发的管理和控制的系统和方法。 公开了网络设备和工具优化器以及相关的系统和方法，以改善网络监视环境中的网络源和目的地工具之间的分组转发。 公开的网络设备和工具优化器可以包括图形用户界面（GUI），用户可以通过图形用户界面（GUI）创建和修改过滤器并且选择相关联的过滤标准以将分组从输入端口转发到输出端口。 网络设备和工具优化器还可以自动生成过滤器规则并将其应用到适当的过滤器引擎，以便数据包按照用户的需要进行转发。 GUI也可以配置为提供其他功能。
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公开(公告)号：US08462781B2
公开(公告)日：2013-06-11
申请号：US13080906
申请日：2011-04-06
CPC分类号： H04L45/7453 , H04L43/028 , H04L43/12
摘要： Systems and methods are disclosed for in-line removal of duplicate network packets in network packet streams operating at high speeds (e.g., 1-10 Gbps and above). A hash generator applies at least one hash algorithm to incoming packets to form one or more different hash values. The packet deduplication systems and methods then use the one or more hash values for each incoming packet to identify data stored for previously received backs and use the identified data to determine if incoming packets are duplicate packets. Duplicate packets are then removed from the output packet stream thereby reducing duplicate packets for downstream processing. A deduplication window can further be utilized to limit the amount of data stored for previous packets based upon one or more parameters, such as an amount of time that has passed and/or a number of packets for which data has been stored. These parameters can also be selected, configured and/or adjusted to achieve desired operational objectives.
摘要翻译： 公开的系统和方法用于在以高速（例如，1-10Gbps及更高）运行的网络分组流中在线去除重复的网络分组。 散列生成器将至少一个散列算法应用于传入数据包以形成一个或多个不同的哈希值。 然后，分组重复数据删除系统和方法使用每个输入分组的一个或多个散列值来识别为先前接收的背部存储的数据，并使用所识别的数据来确定传入分组是否是重复的分组。 然后从输出分组流中删除重复的分组，从而减少用于下游处理的重复分组。 可以进一步利用重复数据消除窗口来基于一个或多个参数（例如已经经过的时间量和/或数据已被存储的数据包的数量）来限制对先前分组所存储的数据量。 也可以选择，配置和/或调整这些参数以实现所需的操作目标。
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公开(公告)号：US09130818B2
公开(公告)日：2015-09-08
申请号：US13792407
申请日：2013-03-11
申请人： Gregory S. Hilton , Andrew M. Spooner , Franz J. Weller , Patricia A. Abkowitz , Ronald A. Pleshek , Richard G. Jeske , Keith E. Cheney , Charles A. Webb, III , Scott A. Harper
发明人： Gregory S. Hilton , Andrew M. Spooner , Franz J. Weller , Patricia A. Abkowitz , Ronald A. Pleshek , Richard G. Jeske , Keith E. Cheney , Charles A. Webb, III , Scott A. Harper
IPC分类号： H04L12/701 , H04L12/931 , H04L12/24 , H04L12/26
CPC分类号： H04L45/00 , H04L41/0893 , H04L43/00 , H04L49/00
摘要： Systems and methods are disclosed for unified systems of network tool optimizers (NTOs). A NTO supervisor device controls switch fabric circuitry to interconnect a plurality of NTO member devices so that packets received at a source port for one NTO member device can be output to a destination port for a different NTO member device. The NTO supervisor device is further configured to analyze filters for the NTO member devices and to generate filter rules for forwarding packets among the various NTO member devices using the switch fabric circuitry. Further, additional secondary NTO supervisor devices can also be included within the unified NTO system to further expand the system. As such, a plurality of NTO member devices are managed and controlled by one or more NTO supervisor devices to form a highly scalable and efficient unified NTO system.
摘要翻译： 公开了网络工具优化器（NTO）的统一系统的系统和方法。 NTO主管设备控制交换结构电路以互连多个NTO成员设备，使得在一个NTO成员设备的源端口处接收的分组可以被输出到不同NTO成员设备的目的地端口。 NTO管理器设备还被配置为分析NTO成员设备的过滤器，并且生成用于使用交换结构电路在各种NTO成员设备之间转发分组的过滤规则。 此外，还可以在统一的NTO系统中包含附加的辅助NTO监控器设备，以进一步扩展系统。 因此，多个NTO成员设备由一个或多个NTO主管设备管理和控制，以形成高度可扩展且高效的统一NTO系统。
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10.发明授权Systems and methods for precise generation of phase variation in digital signals 有权用于精确生成数字信号相位变化的系统和方法公开(公告)号：US08850259B2
公开(公告)日：2014-09-30
申请号：US12930490
申请日：2011-01-07
申请人： Charles A. Webb, III
发明人： Charles A. Webb, III
CPC分类号： G06F1/025 , G06F1/0321
摘要： Systems and methods are disclosed for precise generation of phase variation in digital signals. The disclosed signal generation embodiments generate a pattern of information bits that represents a digital signal with desired phase variations and transmit this digital pattern at high speed utilizing a serializer to generate a high speed bit stream. The high speed bit stream can be used to generate one or more digital signals, such as clock signals, having desired rates and desired phase variations. In certain embodiments, the desired phase variation can be introduced into the resulting digital signal by removing and/or inserting bits in a digital pattern thereby moving logic transitions (e.g., rising edge transitions, falling edge transitions) as desired within the resulting digital signal. In addition to clock signals, the resulting digital signals generated can be control signals, data signals and/or any other desired digital signal.
摘要翻译： 公开了用于在数字信号中精确地产生相位变化的系统和方法。 所公开的信号生成实施例产生表示具有期望的相位变化的数字信号的信息比特的模式，并且利用串行器高速地传送该数字模式以生成高速比特流。 高速比特流可用于产生具有期望速率和期望相位变化的一个或多个数字信号，例如时钟信号。 在某些实施例中，可以通过去除和/或插入数字图形中的位来将期望的相位变化引入到所得数字信号中，从而根据期望在所得到的数字信号中移动逻辑转换（例如，上升沿转变，下降沿转换）。 除了时钟信号之外，所生成的数字信号可以是控制信号，数据信号和/或任何其它所需的数字信号。
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