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公开(公告)号：US09294081B2
公开(公告)日：2016-03-22
申请号：US14229270
申请日：2014-03-28
IPC分类号： H03K3/00 , H03K17/08 , H03K17/687
CPC分类号： H03K17/08 , H03K17/08122 , H03K17/6872
摘要： An integrated circuit device includes a driver circuit (100) having a pull-up network with a first pull-up transistor (108) coupled to a second pull-up transistor (110) at a first node (VP), and a pull-down network coupled to the pull-up network including a first pull-down transistor (112) coupled to a second pull-down transistor (114) at a second node (VN). A first bias switch (116) is coupled to the first node. A second bias switch (118) is coupled to the second node. A control circuit (104) is coupled to operate the first and second bias switches. The first bias switch is operated to reduce a voltage at the first node during a pull-down cycle of the driver circuit and the second bias switch is operated to reduce a voltage at the second node during a pull-up cycle of the driver circuit.
摘要翻译： 集成电路装置包括具有上拉网络的驱动器电路（100），其中第一上拉晶体管（108）在第一节点（VP）处耦合到第二上拉晶体管（110） 耦合到上拉网络的下拉网络包括在第二节点（VN）处耦合到第二下拉晶体管（114）的第一下拉晶体管（112）。 第一偏置开关（116）耦合到第一节点。 第二偏置开关（118）耦合到第二节点。 耦合控制电路（104）以操作第一和第二偏置开关。 操作第一偏置开关以在驱动器电路的下拉周期期间减小第一节点处的电压，并且在驱动器电路的上拉周期期间操作第二偏置开关以降低第二节点处的电压。
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2.发明授权Switching scheme to extend maximum input voltage range of a DC-to-DC voltage converter 有权开关方案可扩展DC-DC电压转换器的最大输入电压范围公开(公告)号：US09467122B2
公开(公告)日：2016-10-11
申请号：US14472903
申请日：2014-08-29
CPC分类号： H03K3/012 , H02M1/32 , H02M3/158 , H02M3/1588 , Y02B70/1466
摘要： A circuit includes a first transistor having a first current electrode coupled to a first power supply node, a second current electrode coupled to a switching node; a second transistor having a first current electrode coupled to the switching node, a second current electrode coupled to a second power supply node; an inductor having a first terminal coupled to the switching node, a second terminal coupled to an output node; a third transistor having a first current electrode coupled to the output node, a second current electrode coupled to the switching node; a driver circuit configured to transition the switching node from a first voltage to a second voltage by turning on the third transistor to couple the output node to the switching node during a first time period, turning on the first transistor to couple the first power supply node to the switching node during a second time period.
摘要翻译： 电路包括具有耦合到第一电源节点的第一电流电极的第一晶体管，耦合到开关节点的第二电流电极; 第二晶体管，具有耦合到所述开关节点的第一电流电极，耦合到第二电源节点的第二电流电极; 具有耦合到所述交换节点的第一终端的电感器，耦合到输出节点的第二终端; 第三晶体管，其具有耦合到所述输出节点的第一电流电极，耦合到所述交换节点的第二电流电极; 驱动电路，被配置为通过接通第三晶体管将开关节点从第一电压转换到第二电压，以在第一时间周期期间将输出节点耦合到开关节点，导通第一晶体管以耦合第一电源节点 在第二时间段期间到交换节点。
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3.发明申请公开(公告)号：US20150280701A1
公开(公告)日：2015-10-01
申请号：US14229270
申请日：2014-03-28
IPC分类号： H03K17/08 , H03K17/687
CPC分类号： H03K17/08 , H03K17/08122 , H03K17/6872
摘要： An integrated circuit device includes a driver circuit (100) having a pull-up network with a first pull-up transistor (108) coupled to a second pull-up transistor (110) at a first node (VP), and a pull-down network coupled to the pull-up network including a first pull-down transistor (112) coupled to a second pull-down transistor (114) at a second node (VN). A first bias switch (116) is coupled to the first node. A second bias switch (118) is coupled to the second node. A control circuit (104) is coupled to operate the first and second bias switches. The first bias switch is operated to reduce a voltage at the first node during a pull-down cycle of the driver circuit and the second bias switch is operated to reduce a voltage at the second node during a pull-up cycle of the driver circuit.
摘要翻译： 集成电路装置包括具有上拉网络的驱动器电路（100），其中第一上拉晶体管（108）在第一节点（VP）处耦合到第二上拉晶体管（110） 耦合到上拉网络的下拉网络包括在第二节点（VN）处耦合到第二下拉晶体管（114）的第一下拉晶体管（112）。 第一偏置开关（116）耦合到第一节点。 第二偏置开关（118）耦合到第二节点。 耦合控制电路（104）以操作第一和第二偏置开关。 操作第一偏置开关以在驱动器电路的下拉周期期间减小第一节点处的电压，并且在驱动器电路的上拉周期期间操作第二偏置开关以降低第二节点处的电压。
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公开(公告)号：US06658245B2
公开(公告)日：2003-12-02
申请号：US09818337
申请日：2001-03-28
申请人： Junsong Li , Charles E. Seaberg , Jie Su
发明人： Junsong Li , Charles E. Seaberg , Jie Su
IPC分类号： H04B110
CPC分类号： H04B1/1036
摘要： A radio receiver (100) has an IF (intermediate frequency) filter (200) for dynamically adjusting its intermediate frequency. The filter (200) includes a filter bank (301), power/amplitude estimator circuits (308, 310, 312), and weighting circuits (314, 316, 318). The filter bank (301) generates sub-bands, each sub-band having a predetermined frequency range. The power/amplitude estimators (308, 310, 312) provide an estimated power/amplitude in each sub-band. A filter control (320) uses the power/amplitude estimates to determine a percentage of each sub-band signal that is permitted to be coupled a summation circuit (319). The summation circuit (319) sums the weighted sub-band signals to provide a filtered output signal to a demodulator (212).
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公开(公告)号：US08537625B2
公开(公告)日：2013-09-17
申请号：US13045294
申请日：2011-03-10
申请人： Ravindraraj Ramaraju , Shayan Zhang , Kenneth R. Burch , Charles E. Seaberg , Andrew C. Russell
发明人： Ravindraraj Ramaraju , Shayan Zhang , Kenneth R. Burch , Charles E. Seaberg , Andrew C. Russell
IPC分类号： G11C11/412
CPC分类号： G11C11/417 , G11C5/147 , G11C11/412 , G11C29/021 , G11C29/028
摘要： A voltage regulator for a memory that regulates a voltage provided to the memory cells based on a measured leakage current from a second set of memory cells. In one embodiment, based on the measured leakage current, the voltage to the cells is raised or lowered to control the amount of leakage current from the cells.
摘要翻译： 一种用于存储器的电压调节器，其基于来自第二组存储器单元的测量的泄漏电流来调节提供给存储器单元的电压。 在一个实施例中，基于测量的漏电流，提高或降低对电池的电压以控制来自电池的泄漏电流的量。
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公开(公告)号：US06760386B2
公开(公告)日：2004-07-06
申请号：US09916915
申请日：2001-07-27
申请人： Junsong Li , Jon D. Hendrix , Charles E. Seaberg
发明人： Junsong Li , Jon D. Hendrix , Charles E. Seaberg
IPC分类号： H04L102
CPC分类号： H04B7/0865 , H04B1/1081 , H04B1/28 , H04B7/0871 , H04B7/0891
摘要： Embodiments of the present invention relate generally to receivers. One embodiment relates to a digital FM receiver having multiple sensors (e.g. antennas). In one embodiment, the digital receiver includes a baseband unit having a channel processing unit. In one embodiment, the channel processing unit is capable of calculating or estimating a phase difference between the incoming signals prior to combining them. One embodiment uses phase estimation method for diversity combining the signals while another embodiment utlizes a hybrid phase lock loop method. Also, some embodiments of the present invention provide for echo-cancelling after diversity combining. An alternate embodiment of the channel processing unit utilizes a space-time unit to diversity combine and provide echo cancelling for the incoming signals. Other embodiments of the present invention allow for the incoming signals from the multiple antennas to pass through the baseband unit uncombined, where the incoming signals may have different data formats.
摘要翻译： 本发明的实施例一般涉及接收机。 一个实施例涉及具有多个传感器（例如，天线）的数字FM接收机。 在一个实施例中，数字接收机包括具有信道处理单元的基带单元。 在一个实施例中，信道处理单元能够在组合它们之前计算或估计输入信号之间的相位差。 一个实施例使用相位估计方法用于组合信号的分集，而另一实施例利用混合锁相环方法。 此外，本发明的一些实施例提供了在分集组合之后的回波消除。 信道处理单元的另一实施例利用时空单元进行分集组合，并为输入信号提供回波消除。 本发明的其他实施例允许来自多个天线的输入信号通过未组合的基带单元，其中输入信号可以具有不同的数据格式。
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公开(公告)号：US20100207687A1
公开(公告)日：2010-08-19
申请号：US12372997
申请日：2009-02-18
IPC分类号： G05F1/10
摘要： A circuit has a first transistor having a first current electrode coupled to a first supply voltage terminal and a second current electrode coupled to a virtual supply voltage node. A second transistor has a first current electrode coupled to the first supply voltage terminal and a control electrode coupled to the virtual supply voltage node. A first load has an input and has an output coupled to a second current electrode of the second transistor. A third transistor has a control electrode coupled to the output of the first load. A second load has an input coupled to the first supply voltage terminal, and has an output that is coupled to both a control electrode of the first transistor and a first current electrode of the third transistor. The virtual supply voltage node provides an operating voltage to a circuit module that alternates between normal and drowsy operating modes.
摘要翻译： 电路具有第一晶体管，其具有耦合到第一电源电压端子的第一电流电极和耦合到虚拟电源电压节点的第二电流电极。 第二晶体管具有耦合到第一电源电压端子的第一电流电极和耦合到虚拟电源电压节点的控制电极。 第一负载具有输入并且具有耦合到第二晶体管的第二电流电极的输出。 第三晶体管具有耦合到第一负载的输出的控制电极。 第二负载具有耦合到第一电源电压端子的输入，并且具有耦合到第一晶体管的控制电极和第三晶体管的第一电流电极两者的输出。 虚拟电源电压节点向在正常和困倦的操作模式之间交替的电路模块提供工作电压。
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公开(公告)号：US20120230126A1
公开(公告)日：2012-09-13
申请号：US13045294
申请日：2011-03-10
申请人： Ravindraraj Ramaraju , Shayan Zhang , Kenneth R. Burch , Charles E. Seaberg , Andrew C. Russell
发明人： Ravindraraj Ramaraju , Shayan Zhang , Kenneth R. Burch , Charles E. Seaberg , Andrew C. Russell
CPC分类号： G11C11/417 , G11C5/147 , G11C11/412 , G11C29/021 , G11C29/028
摘要： A voltage regulator for a memory that regulates a voltage provided to the memory cells based on a measured leakage current from a second set of memory cells. In one embodiment, based on the measured leakage current, the voltage to the cells is raised or lowered to control the amount of leakage current from the cells.
摘要翻译： 一种用于存储器的电压调节器，其基于来自第二组存储器单元的测量的泄漏电流来调节提供给存储器单元的电压。 在一个实施例中，基于测量的漏电流，提高或降低对电池的电压以控制来自电池的泄漏电流的量。
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公开(公告)号：US07825720B2
公开(公告)日：2010-11-02
申请号：US12372997
申请日：2009-02-18
IPC分类号： G05F1/10
摘要： A circuit has a first transistor having a first current electrode coupled to a first supply voltage terminal and a second current electrode coupled to a virtual supply voltage node. A second transistor has a first current electrode coupled to the first supply voltage terminal and a control electrode coupled to the virtual supply voltage node. A first load has an input and has an output coupled to a second current electrode of the second transistor. A third transistor has a control electrode coupled to the output of the first load. A second load has an input coupled to the first supply voltage terminal, and has an output that is coupled to both a control electrode of the first transistor and a first current electrode of the third transistor. The virtual supply voltage node provides an operating voltage to a circuit module that alternates between normal and drowsy operating modes.
摘要翻译： 电路具有第一晶体管，其具有耦合到第一电源电压端子的第一电流电极和耦合到虚拟电源电压节点的第二电流电极。 第二晶体管具有耦合到第一电源电压端子的第一电流电极和耦合到虚拟电源电压节点的控制电极。 第一负载具有输入并且具有耦合到第二晶体管的第二电流电极的输出。 第三晶体管具有耦合到第一负载的输出的控制电极。 第二负载具有耦合到第一电源电压端子的输入，并且具有耦合到第一晶体管的控制电极和第三晶体管的第一电流电极两者的输出。 虚拟电源电压节点向在正常和困倦的操作模式之间交替的电路模块提供工作电压。
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公开(公告)号：US07493179B2
公开(公告)日：2009-02-17
申请号：US10105650
申请日：2002-03-25
摘要： Embodiments of the present invention relate generally to digital volume control in digital audio systems. One embodiment relates to a digital audio system having a digital audio processor and a digital volume control coupled to the digital audio processor. The digital volume control includes a feedback loop having an attenuator, and error determination unit, and a filter. The feedback loop determines the attenuation error and shifts the attenuation error beyond a predetermined digital audio range. The output of the digital volume control maintains a substantially constant SNR and THD with respect to the level attenuation over the predetermined digital audio range.
摘要翻译： 本发明的实施例一般涉及数字音频系统中的数字音量控制。 一个实施例涉及具有耦合到数字音频处理器的数字音频处理器和数字音量控制的数字音频系统。 数字音量控制包括具有衰减器，误差确定单元和滤波器的反馈回路。 反馈环路确定衰减误差并将衰减误差移动超过预定的数字音频范围。 数字音量控制的输出相对于预定数字音频范围上的电平衰减保持基本恒定的SNR和THD。
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