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1.发明授权Digital storage element architecture comprising integrated 4-to-1 multiplexer functionality 有权数字存储元件架构包括集成的4对1复用器功能公开(公告)号：US07274233B2
公开(公告)日：2007-09-25
申请号：US11171535
申请日：2005-06-30
IPC分类号： H03K3/356
CPC分类号： H03K3/0372 , G01R31/318594 , G06F1/06 , G06F9/30141 , G06F9/3867 , G11C19/00 , G11C29/32 , G11C2029/3202
摘要： A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port, the data input ports coupled to a four-input, one-output multiplexer adapted to receive the functional data signals and to selectively output one of the functional data signals. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping.
摘要翻译： 数字存储元件包括主透明锁存器，其从数据输入端口接收功能数据信号并从扫描输入端口扫描数据信号，数据输入端口耦合到四输入单输出多路复用器，适用于接收功能数据信号 并且选择性地输出功能数据信号之一。 数字存储元件还包括耦合到主透明锁存器的从透明锁存器，从属透明锁存器包括专用功能数据和扫描数据输出端口。 当在扫描模式下操作时，从属透明锁存器使用第一时钟信号，并且主透明锁存器使用第二时钟信号，其中第一和第二时钟信号是不重叠的。
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2.发明授权Digital storage element architecture comprising dual scan clocks and gated scan output 有权数字存储元件架构包括双扫描时钟和门控扫描输出公开(公告)号：US07596732B2
公开(公告)日：2009-09-29
申请号：US11171537
申请日：2005-06-30
IPC分类号： G01R31/28
CPC分类号： G01R31/318544
摘要： A digital storage element (e.g., a flip-flop or a latch) includes a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch includes dedicated functional data and scan data output ports. The digital storage element operates in a functional mode and in a scan mode. While in the scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch. The first and second clock signals are non-overlapping and, as such, avoid the digital storage element from creating hold violations.
摘要翻译： 数字存储元件（例如，触发器或锁存器）包括主透明锁存器，其从数据输入端口接收功能数据，并从耦合到主透明锁存器的扫描输入端口和从属透明锁存器扫描数据。 从机透明锁存器包括专用功能数据和扫描数据输出端口。 数字存储元件以功能模式和扫描模式工作。 在扫描模式下，从属透明锁存器使用第一个时钟信号，主器件透明锁存器使用第二个时钟信号。 第一和第二时钟信号是不重叠的，因此避免数字存储元件造成持续违规。
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公开(公告)号：US07345518B2
公开(公告)日：2008-03-18
申请号：US11171612
申请日：2005-06-30
IPC分类号： H03K3/289
CPC分类号： G11C29/32 , G01R31/318552 , G01R31/318575 , G01R31/31858 , G11C29/48 , G11C2029/3202
摘要： A digital storage element comprises a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. The master and slave transparent latches have opposite transparent polarities when in a functional mode and have the same polarities (e.g., positive level sense) when in a scan mode. The transparent polarity of a transparent latch defines the state of a clock to that latch for which the transparent latch is transparent.
摘要翻译： 数字存储元件包括主透明锁存器，其从数据输入端口接收功能数据，并从耦合到主透明锁存器的扫描输入端口和从属透明锁存器扫描数据。 从机透明锁存器包括专用功能数据和扫描数据输出端口。 当处于扫描模式时，主功能模式和从属透明锁存器在功能模式下具有相反的透明极性，并具有相同的极性（例如，正电平感测）。 透明锁定器的透明极性限定了透明闩锁为透明闩锁的锁存器的时钟状态。
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4.发明授权Digital storage element architecture comprising integrated 2-to-1 multiplexer functionality 有权数字存储元件架构包括集成的2对1复用器功能公开(公告)号：US08692592B2
公开(公告)日：2014-04-08
申请号：US11172534
申请日：2005-06-30
IPC分类号： H03K21/00
CPC分类号： G11C29/48 , G11C29/32 , G11C2029/3202
摘要： A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port. The data input ports are coupled to a two-input, one-output multiplexer adapted to receive the functional data signals and to selectively output one of the functional data signals. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping.
摘要翻译： 数字存储元件包括从数据输入端口接收功能数据信号并从扫描输入端口扫描数据信号的主透明锁存器。 数据输入端口耦合到双输入单输出多路复用器，其适于接收功能数据信号并选择性地输出功能数据信号之一。 数字存储元件还包括耦合到主透明锁存器的从透明锁存器，从属透明锁存器包括专用功能数据和扫描数据输出端口。 当在扫描模式下操作时，从属透明锁存器使用第一时钟信号，并且主透明锁存器使用第二时钟信号，其中第一和第二时钟信号是不重叠的。
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5.发明授权Digital storage element architecture comprising integrated multiplexer and reset functionality 有权包括集成多路复用器和复位功能的数字存储元件架构公开(公告)号：US07274234B2
公开(公告)日：2007-09-25
申请号：US11171540
申请日：2005-06-30
IPC分类号： H03K3/289
CPC分类号： H03K3/0372 , G01R31/318575 , G01R31/318594 , G06F9/30141 , G06F9/3867 , G11C29/32 , G11C2029/3202
摘要： A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port, the data input ports coupled to a four-input, one-output multiplexer that receives the functional data signals and selectively outputs one of the functional data signals. The element comprises a slave transparent latch coupled to the master transparent latch and comprising dedicated functional and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping. A first transistor is coupled to the master transparent latch and a second transistor is coupled to the slave transparent latch. When activated, the first or second transistor resets the element.
摘要翻译： 数字存储元件包括主透明锁存器，其从数据输入端口接收功能数据信号并从扫描输入端口扫描数据信号，数据输入端口耦合到四输入单输出多路复用器，其接收功能数据信号， 选择性地输出功能数据信号之一。 该元件包括耦合到主透明锁存器并且包括专用功能和扫描数据输出端口的从透明锁存器。 当在扫描模式下操作时，从属透明锁存器使用第一时钟信号，并且主透明锁存器使用第二时钟信号，其中第一和第二时钟信号是不重叠的。 第一晶体管耦合到主透明锁存器，第二晶体管耦合到从透明锁存器。 当被激活时，第一或第二晶体管复位元件。
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公开(公告)号：US07487417B2
公开(公告)日：2009-02-03
申请号：US11171528
申请日：2005-06-30
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/318575 , G01R31/318594
摘要： A digital storage element (e.g., a flip-flop or a latch) comprise a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. A clock gating element is also included that gates off a clock to the slave latch, and not the master transparent latch, based on an enable signal that is asserted to disable use of the digital storage element.
摘要翻译： 数字存储元件（例如，触发器或锁存器）包括主透明锁存器，其从数据输入端口接收功能数据，并从耦合到主透明锁存器的扫描输入端口和从属透明锁存器扫描数据。 从机透明锁存器包括专用功能数据和扫描数据输出端口。 还包括时钟门控元件，其基于被断言以禁用数字存储元件的使用的使能信号，将时钟关闭到从锁存器，而不是主器件透明锁存器。
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公开(公告)号：US07425859B2
公开(公告)日：2008-09-16
申请号：US11758900
申请日：2007-06-06
IPC分类号： H03K3/13
CPC分类号： H03K5/135 , H03K2005/00293
摘要： An apparatus for generating pulses includes: (a) A delay unit having an input delay locus for receiving a delay unit input signal and an output delay locus for presenting an output delay signal. The delay unit output signal is delayed by a delay interval with respect to the input delay signal. (B) A latch coupled with the delay unit to selectively keep the delay unit input signal at at least one predetermined signal level.
摘要翻译： 一种用于产生脉冲的装置包括：（a）具有用于接收延迟单元输入信号的输入延迟轨迹和用于呈现输出延迟信号的输出延迟轨迹的延迟单元。 延迟单元输出信号延迟相对于输入延迟信号的延迟间隔。 （B）与延迟单元耦合的锁存器，以选择性地将延迟单元输入信号保持在至少一个预定信号电平。
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8.发明授权Digital storage element architecture comprising dual scan clocks and preset functionality 有权包括双扫描时钟和预置功能的数字存储元件架构公开(公告)号：US07375567B2
公开(公告)日：2008-05-20
申请号：US11172242
申请日：2005-06-30
IPC分类号： H03K3/356
CPC分类号： H03K3/35625 , H03K5/1515
摘要： A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and comprises a master feedback loop with a first transistor coupled to the master feedback loop. The first transistor also is coupled to electrical ground. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports, a slave feedback loop and a second transistor coupled to the slave feedback loop. The second transistor is coupled to electrical ground. When a clock signal is in a first state, the first single transistor is activated to preset the digital storage element. When the clock signal is in a second state, the second single transistor is activated to preset the digital storage element.
摘要翻译： 一种数字存储元件，包括主透明锁存器，其从数据输入端口接收功能数据并从扫描输入端口扫描数据，并且包括主反馈回路，其具有耦合到主反馈回路的第一晶体管。 第一晶体管也耦合到电接地。 数字存储元件还包括耦合到主透明锁存器的从透明锁存器，从属透明锁存器包括专用功能数据和扫描数据输出端口，从反馈环路和耦合到从属反馈回路的第二晶体管。 第二晶体管耦合到电接地。 当时钟信号处于第一状态时，第一单晶体管被激活以预设数字存储元件。 当时钟信号处于第二状态时，第二单晶体管被激活以预设数字存储元件。
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公开(公告)号：US07644383B2
公开(公告)日：2010-01-05
申请号：US11172284
申请日：2005-06-30
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A system and method for repairing crosstalk delays are disclosed herein. By modeling the change in effective capacitance, one may determine the delay attributable to crosstalk, and upsize cells in the failing net according to a mathematical formula in order to counter the delay.
摘要翻译： 本文公开了一种用于修复串扰延迟的系统和方法。 通过对有效电容的变化进行建模，可以根据数学公式确定归因于串扰的延迟，并根据数学公式升高故障网络中的单元，以抵消延迟。
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公开(公告)号：US07626850B2
公开(公告)日：2009-12-01
申请号：US11736400
申请日：2007-04-17
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： Various systems and methods for implementing memory devices are disclosed. For example, some embodiments of the present invention provide sub-threshold memory devices that include a differential bit cell. Such a differential bit cell includes two PMOS transistors, two NMOS transistors, and two inverters. The source of the first PMOS transistor and the source of the second PMOS transistor are electrically coupled to a bit line input, and the source of the first NMOS transistor and the source of the second NMOS transistor are electrically coupled to the bit line input. The gate of the first NMOS transistor and the gate of the second NMOS transistor are electrically coupled to a word line input. The gate of the first PMOS transistor and the gate of the second PMOS transistor are electrically coupled to an inverted version of the word line input. The drain of the first PMOS transistor is electrically coupled to the drain of the first NMOS transistor, and the drain of the second PMOS transistor is electrically coupled to the drain of the second NMOS transistor. In addition, the drain of the first PMOS transistor is electrically coupled to the drain of the second PMOS transistor by the first inverter, and the drain of the second PMOS transistor is electrically coupled to the drain of the first PMOS transistor by the second inverter.
摘要翻译： 公开了用于实现存储器件的各种系统和方法。 例如，本发明的一些实施例提供了包括差分位单元的子阈值存储器件。 这种差分位单元包括两个PMOS晶体管，两个NMOS晶体管和两个反相器。 第一PMOS晶体管的源极和第二PMOS晶体管的源极电耦合到位线输入，并且第一NMOS晶体管的源极和第二NMOS晶体管的源极电耦合到位线输入。 第一NMOS晶体管的栅极和第二NMOS晶体管的栅极电耦合到字线输入。 第一PMOS晶体管的栅极和第二PMOS晶体管的栅极电耦合到字线输入的反相版本。 第一PMOS晶体管的漏极电耦合到第一NMOS晶体管的漏极，并且第二PMOS晶体管的漏极电耦合到第二NMOS晶体管的漏极。 此外，第一PMOS晶体管的漏极由第一反相器电耦合到第二PMOS晶体管的漏极，并且第二PMOS晶体管的漏极由第二反相器电耦合到第一PMOS晶体管的漏极。
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