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1.发明授权公开(公告)号：US06211051B1
公开(公告)日：2001-04-03
申请号：US09292079
申请日：1999-04-14
IPC分类号： H01L213065
CPC分类号： H01L21/31116 , H01L21/76816 , H01L23/485 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： A method of fabricating contacts to device elements of an integrated circuit on a semiconductor substrate that includes: (a) using a plasma process to form a first hole in the material above a first portion of the device, wherein the first hole has a depth and a width at the end of the plasma process, and wherein the first hole has an aspect ratio at the end of the plasma process defined by its depth divided by its width; (b) using a plasma process to form a second hole in the material above a second portion of the device, adjacent to the first portion, wherein the second hole has a depth and a width at the end of the plasma process, and wherein the second hole has an aspect ratio at the end of the plasma process defined by its depth divided by its width; and (c) wherein the aspect ratio of the first hole is substantially equivalent to the aspect ratio of the second hole.
摘要翻译： 一种制造与半导体衬底上的集成电路的器件元件的接触的方法，包括：（a）使用等离子体工艺在所述器件的第一部分上方的材料中形成第一孔，其中所述第一孔具有深度和 等离子体处理结束时的宽度，并且其中第一孔具有由其深度除以其宽度限定的等离子体工艺结束时的纵横比; （b）使用等离子体处理在与第一部分相邻的装置的第二部分上方的材料上形成第二孔，其中第二孔在等离子体工艺的结束时具有深度和宽度，并且其中 第二孔在其深度除以其宽度定义的等离子体工艺结束时具有纵横比; 和（c）其中第一孔的纵横比基本上等于第二孔的纵横比。
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公开(公告)号：US5620573A
公开(公告)日：1997-04-15
申请号：US431355
申请日：1995-04-28
CPC分类号： G03F1/22
摘要： X-ray masks are typically made by depositing and patterning a layer of heavy metal on a thin supporting membrane. The metal layer must have a relatively low and uniform stress to prevent stress-induced deformation of the pattern. Tungsten films having excellent stress characteristics are produced by employing a continuously operating capacitance-based measurement technique to allow adjustment of the deposition conditions in rapid response to changes in stress of the film being deposited. The stress gradients in the film are further reduced by transferring heat from the membrane as the metal is deposited thereon.
摘要翻译： 通常通过在薄的支撑膜上沉积和图案化重金属层来制造X射线掩模。 金属层必须具有相对较低且均匀的应力以防止图案的应力引起的变形。 通过采用连续操作的基于电容的测量技术来产生具有优异应力特性的钨膜，以便能够快速响应沉积膜的应力变化来调节沉积条件。 当金属沉积在膜上时，通过从膜传递热量来进一步降低膜中的应力梯度。
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3.发明授权Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same 有权具有层间对准标记的半导体晶片及其制造方法公开(公告)号：US06288454B1
公开(公告)日：2001-09-11
申请号：US09602797
申请日：2000-06-23
IPC分类号： H01L23544
CPC分类号： G03F9/708 , G03F9/7084 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A method of creating a layer-to-layer alignment mark in a semiconductor wafer includes the step of depositing a first conductor layer on a substrate associated with the semiconductor wafer. The method also includes the step of fabricating a number of alignment trenches in the first conductor layer. Moreover, the method includes the step of depositing a first insulator layer on the first conductor layer so as to fill the number of alignment trenches. Yet further, the method includes the step of removing material associated with the first insulator layer from the number of alignment trenches such that an upper surface of the first conductor layer and an upper surface of the first insulator layer define a first alignment step feature which possesses a predetermined height. The method also includes the step of depositing a second conductor layer on the semiconductor wafer subsequent to the removing step. A semiconductor wafer is also disclosed.
摘要翻译： 在半导体晶片中形成层间对准标记的方法包括在与半导体晶片相关联的衬底上沉积第一导体层的步骤。 该方法还包括在第一导体层中制造多个对准沟槽的步骤。 此外，该方法包括在第一导体层上沉积第一绝缘体层以填充对准沟槽的数量的步骤。 此外，该方法包括以下步骤：从对准沟槽的数量去除与第一绝缘体层相关联的材料，使得第一导体层的上表面和第一绝缘体层的上表面限定第一对准步骤特征，其具有 一个预定的高度。 该方法还包括在去除步骤之后在半导体晶片上沉积第二导体层的步骤。 还公开了半导体晶片。
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4.发明授权Confinement device for use in dry etching of substrate surface and method of dry etching a wafer surface 失效用于衬底表面的干蚀刻的限制装置和干式蚀刻晶片表面的方法公开(公告)号：US06852243B2
公开(公告)日：2005-02-08
申请号：US09884805
申请日：2001-06-18
IPC分类号： H01J37/32 , H01L21/302
CPC分类号： H01J37/32623
摘要： A confinement device for operative arrangement within a substrate etching chamber, having a lower surface of the device generally arranged over a substrate outer top surface such that a gap-spacing therebetween is generally equidistant. This spacing is less than a sheath thickness for the plasma, preferably less than ⅓rd of an inner width of an aperture through the lower surface of the device. The aperture, sized preferably greater than 3 times the sheath thickness, is in communication with a channel of the device in which an etchant gas can be confined for reaction to selectively etch a localized area in the substrate outer top surface generally below the aperture. A system for dry etching an IC wafer includes a substrate etching chamber and a confinement device. The etchant gas may be a plasma induced and sustained by RF energy, a microwave source, or other source, as designed. And, a method is included for selectively etching a localized area in a substrate outer top surface, having the steps of: arranging a lower surface of a confinement device over the outer top surface, leaving a spacing therebetween, so that an aperture through said lower surface is located generally above the localized area (the spacing may cover the whole of the outer top surface, an area on which microcircuits are fabricated, or some other portion of the outer top surface); and providing an etchant gas to a channel in the device that is in communication with the aperture.
摘要翻译： 一种用于在衬底蚀刻室内操作地布置的限制装置，其具有通常布置在衬底外顶表面上的器件的下表面，使得它们之间的间隙间隔大致等距。 该间隔小于等离子体的护套厚度，优选小于穿过器件下表面的孔的内部宽度的1/3。 尺寸优选大于皮套厚度的3倍的孔径与装置的通道连通，其中可以限制蚀刻剂气体用于反应以选择性地蚀刻通常在孔下方的基板外顶表面中的局部区域。 用于干蚀刻IC晶片的系统包括基板蚀刻室和限制装置。 蚀刻剂气体可以是被设计的由RF能量，微波源或其它源引起和维持的等离子体。 并且，包括用于选择性蚀刻衬底外顶表面中的局部区域的方法，具有以下步骤：将限制装置的下表面布置在外顶表面上，留下间隔，使得通过所述下表面的孔 表面通常位于局部区域的上方（该间隔可以覆盖整个外顶表面，其上制造微电路的区域，或外顶表面的一些其它部分）; 以及向与所述孔连通的装置中的通道提供蚀刻剂气体。
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5.发明授权Confinement device for use in dry etching of substrate surface and method of dry etching a wafer surface 有权用于衬底表面的干蚀刻的限制装置和干式蚀刻晶片表面的方法公开(公告)号：US06261406B1
公开(公告)日：2001-07-17
申请号：US09228906
申请日：1999-01-11
IPC分类号： H01L213065
CPC分类号： H01J37/32623
摘要： A confinement device for operative arrangement within a substrate etching chamber, having a lower surface of the device generally arranged over a substrate outer top surface such that a gap-spacing therebetween is generally equidistant. This spacing is less than a sheath thickness for the plasma, preferably less than ⅓rd of an inner width of an aperture through the lower surface of the device. The aperture, sized preferably greater than 3 times the sheath thickness, is in communication with a channel of the device in which an etchant gas can be confined for reaction to selectively etch a localized area in the substrate outer top surface generally below the aperture. A system for dry etching an IC wafer includes a substrate etching chamber and a confinement device. The etchant gas may be a plasma induced and sustained by RF energy, a microwave source, or other source, as designed. And, a method is included for selectively etching a localized area in a substrate outer top surface, having the steps of: arranging a lower surface of a confinement device over the outer top surface, leaving a spacing therebetween, so that an aperture through said lower surface is located generally above the localized area (the spacing may cover the whole of the outer top surface, an area on which microcircuits are fabricated, or some other portion of the outer top surface); and providing an etchant gas to a channel in the device that is in communication with the aperture.
摘要翻译： 一种用于在衬底蚀刻室内操作地布置的限制装置，其具有通常布置在衬底外顶表面上的器件的下表面，使得它们之间的间隙间隔大致等距。 该间隔小于等离子体的护套厚度，优选小于穿过器件下表面的孔的内宽度的第1/3。 尺寸优选大于皮套厚度的3倍的孔径与装置的通道连通，其中可以限制蚀刻剂气体用于反应以选择性地蚀刻通常在孔下方的基板外顶表面中的局部区域。 用于干蚀刻IC晶片的系统包括基板蚀刻室和限制装置。 蚀刻剂气体可以是被设计的由RF能量，微波源或其它源引起和维持的等离子体。 并且，包括用于选择性蚀刻衬底外顶表面中的局部区域的方法，具有以下步骤：将限制装置的下表面布置在外顶表面上，留下间隔，使得通过所述下表面的孔 表面通常位于局部区域的上方（该间隔可以覆盖整个外顶表面，其上制造微电路的区域，或外顶表面的一些其它部分）; 以及向与所述孔连通的装置中的通道提供蚀刻剂气体。
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6.发明授权Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same 有权具有层间对准标记的半导体晶片及其制造方法
公开(公告)号：US6136662A
公开(公告)日：2000-10-24
申请号：US311253
申请日：1999-05-13
IPC分类号： G03F9/00 , H01L23/544 , H01L21/76 , H01L21/302 , H01L21/4763
CPC分类号： G03F9/708 , G03F9/7084 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S438/975
摘要： A method of creating a layer-to-layer alignment mark in a semiconductor wafer includes the step of depositing a first conductor layer on a substrate associated with the semiconductor wafer. The method also includes the step of fabricating a number of alignment trenches in the first conductor layer. Moreover, the method includes the step of depositing a first insulator layer on the first conductor layer so as to fill the number of alignment trenches. Yet further, the method includes the step of removing material associated with the first insulator layer from the number of alignment trenches such that an upper surface of the first conductor layer and an upper surface of the first insulator layer define a first alignment step feature which possesses a predetermined height. The method also includes the step of depositing a second conductor layer on the semiconductor wafer subsequent to the removing step. A semiconductor wafer is also disclosed.
摘要翻译： 在半导体晶片中形成层间对准标记的方法包括在与半导体晶片相关联的衬底上沉积第一导体层的步骤。 该方法还包括在第一导体层中制造多个对准沟槽的步骤。 此外，该方法包括在第一导体层上沉积第一绝缘体层以填充对准沟槽的数量的步骤。 此外，该方法包括以下步骤：从对准沟槽的数量去除与第一绝缘体层相关联的材料，使得第一导体层的上表面和第一绝缘体层的上表面限定第一对准步骤特征，其具有 一个预定的高度。 该方法还包括在去除步骤之后在半导体晶片上沉积第二导体层的步骤。 还公开了半导体晶片。
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