公开(公告)号：US20130194874A1

公开(公告)日：2013-08-01

申请号：US13755606

申请日：2013-01-31

申请人： Fuchen Mu ,  Chen He ,  Yanzhuo Wang

发明人： Fuchen Mu ,  Chen He ,  Yanzhuo Wang

IPC分类号： G11C16/06

CPC分类号： G11C16/06 ,  G11C16/3404 ,  G11C16/349

摘要： Methods and systems are disclosed for dynamic healing of non-volatile memory (NVM) cells within NVM systems. The dynamic healing embodiments described herein relax damage within tunnel dielectric layers for NVM cells that occurs over time from charges (e.g., holes and/or electrons) becoming trapped within these tunnel dielectric layers. NVM operations with respect to which dynamic healing processes can be applied include, for example, erase operations, program operations, and read operations. For example, dynamic healing can be applied where performance for the NVM system degrades beyond a selected performance level for an NVM operation, such as elevated erase/program pulse counts for erase/program operations and bit errors for read operations. A variety of healing techniques can be applied, such as drain stress processes, gate stress processes, and/or other desired healing techniques.

摘要翻译： 公开了用于NVM系统内的非易失性存储器（NVM）单元的动态愈合的方法和系统。 本文描述的动态愈合实施例在电荷（例如，空穴和/或电子）被俘获在这些隧道电介质层内的时间内，随着时间的推移而在NVM电池的隧道电介质层内松弛损伤。 关于可以应用哪些动态恢复过程的NVM操作包括例如擦除操作，程序操作和读取操作。 例如，在NVM系统的性能下降到NVM操作的选定性能水平之外，例如擦除/编程操作的擦除/编程脉冲计数升高以及读取操作的位错误，可以应用动态恢复。 可以应用各种愈合技术，例如排水应力过程，门应力过程和/或其他所需的愈合技术。

公开(公告)号：US09030883B2

公开(公告)日：2015-05-12

申请号：US13942814

申请日：2013-07-16

申请人： Chen He ,  Yanzhuo Wang ,  Fuchen Mu

发明人： Chen He ,  Yanzhuo Wang ,  Fuchen Mu

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/06 ,  G11C7/04 ,  G11C16/16

摘要： Methods and systems are disclosed for adaptive erase recovery of non-volatile memory (NVM) cells within NVM systems. The adaptive erase recovery embodiments adaptively adjust the erase recovery discharge rate and/or discharge time based upon the size of NVM block(s) being erased and operating temperature. In one example embodiment, the erase recovery discharge rate is adjusted by adjusting the number of discharge transistors enabled within the discharge circuitry, thereby adjusting the discharge current for erase recovery. A lookup table is used to store erase recovery discharge rates and/or discharge times associated with NVM block sizes to be recovered and/or operating temperature. By adaptively controlling erase recovery discharge rates and/or times, the disclosed embodiments improve overall erase performance for a wide range of NVM block sizes while avoiding possible damage to high voltage circuitry within the NVM system.

摘要翻译： 公开了用于NVM系统内的非易失性存储器（NVM）单元的自适应擦除恢复的方法和系统。 自适应擦除恢复实施例基于被擦除的NVM块的大小和操作温度自适应地调整擦除恢复放电速率和/或放电时间。 在一个示例性实施例中，通过调节在放电电路内使能的放电晶体管的数量来调整擦除恢复放电率，从而调节用于擦除恢复的放电电流。 查找表用于存储与要恢复的NVM块大小相关联的擦除恢复放电率和/或放电时间和/或工作温度。 通过自适应地控制擦除恢复放电率和/或时间，所公开的实施例提高了宽范围NVM块大小的整体擦除性能，同时避免了对NVM系统内的高电压电路的可能损坏。

公开(公告)号：US20150117112A1

公开(公告)日：2015-04-30

申请号：US14069195

申请日：2013-10-31

申请人： CHEN HE ,  Fuchen Mu ,  Yanzhuo Wang

发明人： CHEN HE ,  Fuchen Mu ,  Yanzhuo Wang

IPC分类号： G11C16/16 ,  G11C16/34

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/14 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345

摘要： A method includes an erase of a plurality of blocks of memory cells in which the memory cells within a block are simultaneously erased. The erase of each block of the plurality of blocks is performed using an erase pulse applied multiple times. The erase pulse is applied to the plurality of blocks in parallel. An erase verify is performed after each application of the erase pulse. After a number applications of the erase pulse, it is determined if a condition comprising one of a group consisting of any memory cell has been more erased than a first predetermined amount and any memory cell has been erased less than a second predetermined amount has been met. If the condition has been met, erasing is continued by applying the erase pulse to the block having the memory cell with the condition independently of the other blocks of the plurality of blocks.

摘要翻译： 一种方法包括擦除其中块内的存储单元被同时擦除的多个存储单元块。 使用多次施加的擦除脉冲来执行多个块中的每个块的擦除。 擦除脉冲并行地施加到多个块。 在每次施加擦除脉冲之后执行擦除验证。 在擦除脉冲的数字应用之后，确定包括任何存储器单元组成的组之一的条件是否已经比第一预定量更多地被擦除，并且已经擦除了小于第二预定量的任何存储单元已被擦除 。 如果满足条件，则通过将擦除脉冲施加到具有独立于多个块的其他块的条件的具有存储器单元的块来继续擦除。

公开(公告)号：US20150023106A1

公开(公告)日：2015-01-22

申请号：US13942814

申请日：2013-07-16

申请人： Chen He ,  Yanzhuo Wang ,  Fuchen Mu

发明人： Chen He ,  Yanzhuo Wang ,  Fuchen Mu

IPC分类号： G11C16/06

CPC分类号： G11C16/06 ,  G11C7/04 ,  G11C16/16

摘要： Methods and systems are disclosed for adaptive erase recovery of non-volatile memory (NVM) cells within NVM systems. The adaptive erase recovery embodiments adaptively adjust the erase recovery discharge rate and/or discharge time based upon the size of NVM block(s) being erased and operating temperature. In one example embodiment, the erase recovery discharge rate is adjusted by adjusting the number of discharge transistors enabled within the discharge circuitry, thereby adjusting the discharge current for erase recovery. A lookup table is used to store erase recovery discharge rates and/or discharge times associated with NVM block sizes to be recovered and/or operating temperature. By adaptively controlling erase recovery discharge rates and/or times, the disclosed embodiments improve overall erase performance for a wide range of NVM block sizes while avoiding possible damage to high voltage circuitry within the NVM system.

摘要翻译： 公开了用于NVM系统内的非易失性存储器（NVM）单元的自适应擦除恢复的方法和系统。 自适应擦除恢复实施例基于被擦除的NVM块的大小和操作温度自适应地调整擦除恢复放电速率和/或放电时间。 在一个示例性实施例中，通过调节在放电电路内使能的放电晶体管的数量来调整擦除恢复放电率，从而调节用于擦除恢复的放电电流。 查找表用于存储与要恢复的NVM块大小相关联的擦除恢复放电率和/或放电时间和/或工作温度。 通过自适应地控制擦除恢复放电率和/或时间，所公开的实施例提高了宽范围NVM块大小的整体擦除性能，同时避免了对NVM系统内的高电压电路的可能损坏。

公开(公告)号：US09082493B2

公开(公告)日：2015-07-14

申请号：US14069195

申请日：2013-10-31

申请人： Chen He ,  Fuchen Mu ,  Yanzhuo Wang

发明人： Chen He ,  Fuchen Mu ,  Yanzhuo Wang

IPC分类号： G11C11/34 ,  G11C16/16 ,  G11C16/34 ,  G11C16/14 ,  G11C11/56

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/14 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345

摘要： A method includes an erase of a plurality of blocks of memory cells in which the memory cells within a block are simultaneously erased. The erase of each block of the plurality of blocks is performed using an erase pulse applied multiple times. The erase pulse is applied to the plurality of blocks in parallel. An erase verify is performed after each application of the erase pulse. After a number applications of the erase pulse, it is determined if a condition comprising one of a group consisting of any memory cell has been more erased than a first predetermined amount and any memory cell has been erased less than a second predetermined amount has been met. If the condition has been met, erasing is continued by applying the erase pulse to the block having the memory cell with the condition independently of the other blocks of the plurality of blocks.

摘要翻译： 一种方法包括擦除其中块内的存储单元被同时擦除的多个存储单元块。 使用多次施加的擦除脉冲来执行多个块中的每个块的擦除。 擦除脉冲并行地施加到多个块。 在每次施加擦除脉冲之后执行擦除验证。 在擦除脉冲的数字应用之后，确定包括任何存储器单元组成的组之一的条件是否已经比第一预定量更多地被擦除，并且已经擦除了小于第二预定量的任何存储单元已被擦除 。 如果满足条件，则通过将擦除脉冲施加到具有独立于多个块的其他块的条件的具有存储器单元的块来继续擦除。

公开(公告)号：US20150049555A1

公开(公告)日：2015-02-19

申请号：US13965731

申请日：2013-08-13

申请人： Fuchen Mu ,  Chen He ,  Yanzhuo Wang

发明人： Fuchen Mu ,  Chen He ,  Yanzhuo Wang

IPC分类号： G11C16/34 ,  G11C16/14

CPC分类号： G11C16/3459 ,  G11C16/14 ,  G11C16/345

摘要： Methods and systems are disclosed for extended erase protection for non-volatile memory (NVM) cells during embedded erase operations for NVM systems. The embodiments described herein utilize an additional threshold voltage (Vt) check after soft programming operation within an embedded erase operation completes to provide extended erase protection of NVM cells. In particular, the threshold voltages for NVM cells are compared against a threshold voltage (Vt) check voltage (VCHK) level and an additional embedded erase cycle is performed if any NVM cells are found to exceed the threshold voltage (Vt) check voltage (VCHK) level. The threshold voltage (Vt) check voltage (VCHK) level can be, for example, a voltage level that is slightly higher than an erase verify voltage (VEV) level and lower than read voltage level (VR).

摘要翻译： 公开了用于NVM系统的嵌入式擦除操作期间用于非易失性存储器（NVM）单元的扩展擦除保护的方法和系统。 本文描述的实施例在嵌入式擦除操作中的软编程操作完成之后利用额外的阈值电压（Vt）检查，以提供NVM单元的扩展擦除保护。 特别地，NVM单元的阈值电压与阈值电压（Vt）检查电压（VCHK）电平进行比较，并且如果发现任何NVM单元超过阈值电压（Vt）检查电压（VCHK），执行附加的嵌入式擦除周期 ）级别。 阈值电压（Vt）检查电压（VCHK）电平可以是例如略高于擦除验证电压（VEV）电平并低于读取电压电平（VR）的电压电平。

公开(公告)号：US08902667B2

公开(公告)日：2014-12-02

申请号：US13557629

申请日：2012-07-25

申请人： Fuchen Mu ,  Yanzhuo Wang ,  Chen He ,  Richard K. Eguchi

发明人： Fuchen Mu ,  Yanzhuo Wang ,  Chen He ,  Richard K. Eguchi

IPC分类号： G11C11/34

CPC分类号： G11C29/021 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/349 ,  G11C29/028

摘要： Non-volatile memory (NVM) systems and related methods adjust program/erase bias conditions for non-volatile memory (NVM) cells to improve performance and product lifetime of NVM systems. System embodiments include integrated NVM systems having an NVM controller, a bias voltage generator, and an NVM cell array. Further, the NVM systems can store performance degradation information and program/erase bias condition information within storage circuitry. The disclosed embodiments adjust program/erase bias conditions for the NVM cells based upon performance degradation determinations, for example, temperature-based performance degradation determinations and interim verify based performance degradation determinations.

摘要翻译： 非易失性存储器（NVM）系统和相关方法调整非易失性存储器（NVM）单元的编程/擦除偏置条件，以提高NVM系统的性能和产品寿命。 系统实施例包括具有NVM控制器，偏置电压发生器和NVM单元阵列的集成NVM系统。 此外，NVM系统可以在存储电路内存储性能劣化信息和编程/擦除偏置条件信息。 所公开的实施例基于性能劣化确定来调整NVM单元的编程/擦除偏置条件，例如基于温度的性能劣化确定和基于临时验证的性能劣化确定。

公开(公告)号：US09343172B2

公开(公告)日：2016-05-17

申请号：US13965731

申请日：2013-08-13

申请人： Fuchen Mu ,  Chen He ,  Yanzhuo Wang

发明人： Fuchen Mu ,  Chen He ,  Yanzhuo Wang

IPC分类号： G11C11/34 ,  G11C16/34 ,  G11C16/14

CPC分类号： G11C16/3459 ,  G11C16/14 ,  G11C16/345

摘要： Methods and systems are disclosed for extended erase protection for non-volatile memory (NVM) cells during embedded erase operations for NVM systems. The embodiments described herein utilize an additional threshold voltage (Vt) check after soft programming operation within an embedded erase operation completes to provide extended erase protection of NVM cells. In particular, the threshold voltages for NVM cells are compared against a threshold voltage (Vt) check voltage (VCHK) level and an additional embedded erase cycle is performed if any NVM cells are found to exceed the threshold voltage (Vt) check voltage (VCHK) level. The threshold voltage (Vt) check voltage (VCHK) level can be, for example, a voltage level that is slightly higher than an erase verify voltage (VEV) level and lower than read voltage level (VR).

摘要翻译： 公开了用于NVM系统的嵌入式擦除操作期间用于非易失性存储器（NVM）单元的扩展擦除保护的方法和系统。 本文描述的实施例在嵌入式擦除操作中的软编程操作完成之后利用额外的阈值电压（Vt）检查，以提供NVM单元的扩展擦除保护。 特别地，NVM单元的阈值电压与阈值电压（Vt）检查电压（VCHK）电平进行比较，并且如果发现任何NVM单元超过阈值电压（Vt）检查电压（VCHK），执行附加的嵌入式擦除周期 ）级别。 阈值电压（Vt）检查电压（VCHK）电平可以是例如略高于擦除验证电压（VEV）电平且低于读取电压电平（VR）的电压电平。

公开(公告)号：US08995200B1

公开(公告)日：2015-03-31

申请号：US14033622

申请日：2013-09-23

申请人： Fuchen Mu ,  Chen He ,  Yanzhuo Wang

发明人： Fuchen Mu ,  Chen He ,  Yanzhuo Wang

IPC分类号： G11C16/06 ,  G11C7/08

CPC分类号： G11C7/08 ,  G11C7/14 ,  G11C16/14 ,  G11C16/28 ,  G11C16/3459 ,  G11C16/349

摘要： A sense amplifier is configured to sense a current from a selected bit cell of a non-volatile memory array and compare the sensed current to a reference current to determine a logic state stored in the bit cell. A controller is configured to perform a program/erase operation on at least a portion of the memory array to change a logic state of at least one bit cell of the portion of the memory array; determine a number of program/erase pulses applied to the at least one bit cell during the program/erase operation to achieve the change in logic state; and when the number of program/erase pulses exceeds a pulse count threshold, adjust the reference current of the sense amplifier for a subsequent program/erase operation.

摘要翻译： 感测放大器被配置为感测来自非易失性存储器阵列的选定位单元的电流，并将感测的电流与参考电流进行比较，以确定存储在位单元中的逻辑状态。 控制器被配置为在存储器阵列的至少一部分上执行编程/擦除操作以改变存储器阵列的该部分的至少一个比特单元的逻辑状态; 确定在编程/擦除操作期间施加到至少一个位单元的编程/擦除脉冲的数量，以实现逻辑状态的改变; 并且当编程/擦除脉冲的数量超过脉冲计数阈值时，调整读出放大器的参考电流以用于随后的编程/擦除操作。

公开(公告)号：US08964482B2

公开(公告)日：2015-02-24

申请号：US13755606

申请日：2013-01-31

申请人： Fuchen Mu ,  Chen He ,  Yanzhuo Wang

发明人： Fuchen Mu ,  Chen He ,  Yanzhuo Wang

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C16/34

CPC分类号： G11C16/06 ,  G11C16/3404 ,  G11C16/349

摘要： Methods and systems are disclosed for dynamic healing of non-volatile memory (NVM) cells within NVM systems. The dynamic healing embodiments described herein relax damage within tunnel dielectric layers for NVM cells that occurs over time from charges (e.g., holes and/or electrons) becoming trapped within these tunnel dielectric layers. NVM operations with respect to which dynamic healing processes can be applied include, for example, erase operations, program operations, and read operations. For example, dynamic healing can be applied where performance for the NVM system degrades beyond a selected performance level for an NVM operation, such as elevated erase/program pulse counts for erase/program operations and bit errors for read operations. A variety of healing techniques can be applied, such as drain stress processes, gate stress processes, and/or other desired healing techniques.

摘要翻译： 公开了用于NVM系统内的非易失性存储器（NVM）单元的动态愈合的方法和系统。 本文描述的动态愈合实施例在电荷（例如，空穴和/或电子）被俘获在这些隧道电介质层内的时间内，随着时间的推移而在NVM电池的隧道电介质层内松弛损伤。 关于可以应用哪些动态恢复过程的NVM操作包括例如擦除操作，程序操作和读取操作。 例如，在NVM系统的性能下降到NVM操作的选定性能水平之外，例如擦除/编程操作的擦除/编程脉冲计数升高以及读取操作的位错误，可以应用动态恢复。 可以应用各种愈合技术，例如排水应力过程，门应力过程和/或其他所需的愈合技术。