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    Apparatus to implement symmetric single-ended termination in differential voltage-mode drivers
    1.
    发明授权
    Apparatus to implement symmetric single-ended termination in differential voltage-mode drivers 有权
    在差分电压模式驱动器中实现对称单端端接的装置

    公开(公告)号：US08760189B2

    公开(公告)日：2014-06-24

    申请号：US13248485

    申请日：2011-09-29

    申请人： Cheng Zhong ,  Vannam Dang ,  Miao Li ,  Fares K. Maarouf ,  Tirdad Sowlati

    发明人： Cheng Zhong ,  Vannam Dang ,  Miao Li ,  Fares K. Maarouf ,  Tirdad Sowlati

    IPC分类号： H03K17/16

    CPC分类号： H04L25/0274 ,  H04L25/0278

    摘要： A differential voltage mode driver for implementing symmetric single ended termination includes an output driver circuitry having a predefined termination impedance. The differential voltage mode driver also includes an output driver replica having independently controlled first and second portions. The first and second portions are independently controlled to establish a substantially equal on-resistance of the first and the second portions. The output driver replica controls the predefined termination impedance of the output driver circuitry.

    摘要翻译： 用于实现对称单端终端的差分电压模式驱动器包括具有预定义的终端阻抗的输出驱动器电路。 差分电压模式驱动器还包括具有独立控制的第一和第二部分的输出驱动器副本。 独立地控制第一和第二部分以建立第一和第二部分的基本相等的导通电阻。 输出驱动器副本控制输出驱动器电路的预定终止阻抗。

    Apparatus to Implement Symmetric Single-Ended Termination in Differential Voltage-Mode Drivers
    2.
    发明申请
    Apparatus to Implement Symmetric Single-Ended Termination in Differential Voltage-Mode Drivers 有权
    在差分电压模式驱动器中实现对称单端终止的装置

    公开(公告)号：US20130082744A1

    公开(公告)日：2013-04-04

    申请号：US13248485

    申请日：2011-09-29

    申请人： Cheng Zhong ,  Vannam Dang ,  Miao Li ,  Fares K. Maarouf ,  Tirdad Sowlati

    发明人： Cheng Zhong ,  Vannam Dang ,  Miao Li ,  Fares K. Maarouf ,  Tirdad Sowlati

    IPC分类号： H03K3/00

    CPC分类号： H04L25/0274 ,  H04L25/0278

    摘要： A differential voltage mode driver for implementing symmetric single ended termination includes an output driver circuitry having a predefined termination impedance. The differential voltage mode driver also includes an output driver replica having independently controlled first and second portions. The first and second portions are independently controlled to establish a substantially equal on-resistance of the first and the second portions. The output driver replica controls the predefined termination impedance of the output driver circuitry.

    摘要翻译： 用于实现对称单端终端的差分电压模式驱动器包括具有预定义的终端阻抗的输出驱动器电路。 差分电压模式驱动器还包括具有独立控制的第一和第二部分的输出驱动器副本。 独立地控制第一和第二部分以建立第一和第二部分的基本相等的导通电阻。 输出驱动器副本控制输出驱动器电路的预定终止阻抗。

    High speed data testing without high speed bit clock
    3.
    发明授权
    High speed data testing without high speed bit clock 有权
    无高速位时钟的高速数据测试

    公开(公告)号：US08630821B2

    公开(公告)日：2014-01-14

    申请号：US13189926

    申请日：2011-07-25

    申请人： Miao Li ,  Xiaohua Kong ,  Nam V. Dang ,  Cheng Zhong

    发明人： Miao Li ,  Xiaohua Kong ,  Nam V. Dang ,  Cheng Zhong

    IPC分类号： G06F11/30

    CPC分类号： G01R31/3177 ,  G06F1/04 ,  G09G5/006 ,  G09G2350/00 ,  G09G2370/12

    摘要： System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

    摘要翻译： 用于测试高速数据路径而不产生高速位时钟的系统和方法包括从多个数据路径中选择第一高速数据路径进行测试。 在多个数据路径的一个或多个剩余数据路径上驱动相干时钟数据模式，其中相干时钟数据模式与低速基准时钟保持一致。 第一高速数据路径被相干时钟数据模式采样，以产生采样的第一高速数据路径，然后以低速基准时钟的速度进行测试。

    HIGH SPEED DATA TESTING WITHOUT HIGH SPEED BIT CLOCK
    4.
    发明申请
    HIGH SPEED DATA TESTING WITHOUT HIGH SPEED BIT CLOCK 有权
    高速数据测试无高速位时钟

    公开(公告)号：US20130030767A1

    公开(公告)日：2013-01-31

    申请号：US13189926

    申请日：2011-07-25

    申请人： Miao Li ,  Xiaohua Kong ,  Nam V. Dang ,  Cheng Zhong

    发明人： Miao Li ,  Xiaohua Kong ,  Nam V. Dang ,  Cheng Zhong

    IPC分类号： G06F11/30

    CPC分类号： G01R31/3177 ,  G06F1/04 ,  G09G5/006 ,  G09G2350/00 ,  G09G2370/12

    摘要： System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

    摘要翻译： 用于测试高速数据路径而不产生高速位时钟的系统和方法包括从多个数据路径中选择第一高速数据路径进行测试。 在多个数据路径的一个或多个剩余数据路径上驱动相干时钟数据模式，其中相干时钟数据模式与低速基准时钟保持一致。 第一高速数据路径被相干时钟数据模式采样，以产生采样的第一高速数据路径，然后以低速基准时钟的速度进行测试。

    Method and system for determining an end time of uplink back propagation
    5.
    发明授权
    Method and system for determining an end time of uplink back propagation 有权
    用于确定上行链路反向传播的结束时间的方法和系统

    公开(公告)号：US08837310B2

    公开(公告)日：2014-09-16

    申请号：US13259312

    申请日：2010-03-24

    申请人： Dafei Wang ,  Delong Tang ,  Xiaoan Hou ,  Miao Li

    发明人： Dafei Wang ,  Delong Tang ,  Xiaoan Hou ,  Miao Li

    IPC分类号： H04W36/02 ,  H04W28/10 ,  H04L12/801 ,  H04J3/06 ,  H04W28/14 ,  H04W24/00 ,  H04W92/04

    CPC分类号： H04W24/00 ,  H04J3/06 ,  H04L47/34 ,  H04W28/10 ,  H04W28/14 ,  H04W36/02 ,  H04W92/045

    摘要： The invention provides a method and a system for determining an end time of uplink back propagation in a mobile communication system to solve a problem of accurately judging the end time of uplink back propagation, wherein the method includes the following steps: sending data with consecutive sequence numbers in a buffer of a packet data convergence protocol (PDCP) module to a serving gateway (S-GW) via an S1 tunnel; sending data with inconsecutive sequence numbers, which is from data with a first inconsecutive sequence number to last data in the buffer of the PDCP module, to a target base station via an uplink back propagation tunnel; generating an end marker datagram; sending the end marker datagram to the target base station via the uplink back propagation tunnel; and receiving, by the target base station, the end marker datagram and determining that the uplink back propagation has ended.

    摘要翻译： 本发明提供了一种用于确定移动通信系统中上行反向传播的结束时间的方法和系统，以解决精确地判断上行反向传播的结束时间的问题，其中该方法包括以下步骤：以连续序列发送数据 分组数据汇聚协议（PDCP）模块的缓冲器中的号码经由S1隧道传送到服务网关（S-GW）; 将来自具有第一不连续序列号的数据的数据与PDCP模块的缓冲器中的最后数据经由上行链路反向传播隧道发送到目标基站的序列号不一致的数据; 生成结束标记数据报; 通过上行链路反向传播隧道将终端标记数据报发送到目标基站; 并且由目标基站接收终端标记数据报，并确定上行链路反向传播已经结束。

    SYSTEMS AND METHODS FOR DIMMING CONTROL WITH CAPACITIVE LOADS
    7.
    发明申请
    SYSTEMS AND METHODS FOR DIMMING CONTROL WITH CAPACITIVE LOADS 有权
    用电力负载调制控制的系统和方法

    公开(公告)号：US20120268031A1

    公开(公告)日：2012-10-25

    申请号：US13105780

    申请日：2011-05-11

    申请人： Jun Zhou ,  Zhongliang Xiong ,  Miao Li ,  Yaming Cao ,  Qiang Luo ,  Lieyi Fang

    发明人： Jun Zhou ,  Zhongliang Xiong ,  Miao Li ,  Yaming Cao ,  Qiang Luo ,  Lieyi Fang

    IPC分类号： H05B37/02

    CPC分类号： H05B33/0845 ,  H05B33/0815 ,  H05B33/0851 ,  H05B37/02

    摘要： System and method for dimming control. The system includes a system controller including a first controller terminal and a second controller terminal, a transistor including a first transistor terminal, a second transistor terminal and a third transistor terminal, and a resistor including a first resistor terminal and a second resistor terminal. The system controller is configured to generate a first signal at the first controller terminal based on an input signal and to generate a second signal at the second controller terminal based on the first signal. The first transistor terminal is coupled to the second controller terminal. The first resistor terminal is coupled to the second transistor terminal. The second resistor terminal is coupled to the third transistor terminal. The transistor is configured to receive the second signal at the first transistor terminal and to change between two conditions in response to the second signal.

    摘要翻译： 调光控制系统及方法。 该系统包括具有第一控制器端子和第二控制器端子的系统控制器，包括第一晶体管端子，第二晶体管端子和第三晶体管端子的晶体管，以及包括第一电阻端子和第二电阻端子的电阻器。 系统控制器被配置为基于输入信号在第一控制器终端产生第一信号，并且基于第一信号在第二控制器终端产生第二信号。 第一晶体管端子耦合到第二控制器端子。 第一电阻端子耦合到第二晶体管端子。 第二电阻端子耦合到第三晶体管端子。 晶体管被配置为在第一晶体管端子处接收第二信号并响应于第二信号在两个条件之间变化。

    Benzopyrone compounds, preparation method and use thereof
    10.
    发明申请
    Benzopyrone compounds, preparation method and use thereof 有权
    苯并吡喃酮化合物，其制备方法和用途

    公开(公告)号：US20070037876A1

    公开(公告)日：2007-02-15

    申请号：US10573529

    申请日：2004-11-04

    申请人： Changling Liu ,  Aiying Guan ,  Hong Zhang ,  Mingxing Zhang ,  Zhengming Li ,  Miao Li ,  Lin Li ,  Zhinian Li ,  Chunqing Hou

    发明人： Changling Liu ,  Aiying Guan ,  Hong Zhang ,  Mingxing Zhang ,  Zhengming Li ,  Miao Li ,  Lin Li ,  Zhinian Li ,  Chunqing Hou

    IPC分类号： A01N43/16 ,  C07D311/02

    CPC分类号： A01N43/16 ,  C07D311/16

    摘要： The invention relates to pesticide and bactericide, specifically to the benzopyrone compounds and its preparation method and use thereof. The benzopyrone compounds of the invention having general formula (I): The present invention, having good pesticide activity and broad bactericide activity, applied for controlling various pests in plants such as army worm, diamond backmoth and aphid, carmine spider mite, two-spotted spider mite, ladybeetle, mites and mosquito larvae. Various disease in plants can be controlled by the invention and that of grape downy mildew, rice sheath and culm blights rice blast, tomato early blight, tomato late blight wheat leaf rust, wheat leaf blotch, wheat powdery mildew, cucumber powdery mildew, cucumber downy mildew, cucumber grey mold and so on.

    摘要翻译： 本发明涉及农药和杀菌剂，具体涉及苯并吡喃酮化合物及其制备方法和用途。 具有通式（I）的本发明的苯并吡喃酮化合物：本发明具有良好的农药活性和广泛的杀菌活性，用于防治植物中的各种害虫，如陆军虫，金刚石背蛾和蚜虫，胭脂红蜘蛛螨，双斑 蜘蛛螨，瓢虫，螨虫和蚊子幼虫。 本发明可以控制植物中的各种疾病，葡萄霜霉病，稻瘟病，稻瘟病，番茄早疫病，番茄晚疫病小麦叶锈病，小麦叶斑病，小麦白粉病，黄瓜白粉病，黄瓜黄疸 霉变，黄瓜灰霉等。