公开(公告)号：US07420417B2

公开(公告)日：2008-09-02

申请号：US11446204

申请日：2006-06-05

申请人： Cheng-Kuo Lin ,  Wei-Der Chang ,  Yu-Chi Wang

发明人： Cheng-Kuo Lin ,  Wei-Der Chang ,  Yu-Chi Wang

IPC分类号： H03F3/16

CPC分类号： H03F1/301 ,  H03F1/223 ,  H03F3/19 ,  H03F2200/18 ,  H03F2200/294 ,  H03F2200/451

摘要： A two-port dual-gate field-effect transistor for amplifier applications, wherein a self-bias circuit includes a number of passive elements, such as resistors, diodes and capacitors, is utilized to coupled the output of the amplifier with a second gate of the dual-gate device as a bias source, which transforms the conventional three-port cascade topology into a two-port dual-gate device so as to facilitate device testing, modeling, and packaging for discrete device application. The technology improves the RF performance in conventional two-port single-gate HEMT devices, with slight noise figure degradation.

摘要翻译： 一种用于放大器应用的双端口双栅极场效应晶体管，其中自偏置电路包括多个无源元件，例如电阻器，二极管和电容器，用于将放大器的输出端与第二栅极 双栅极器件作为偏置源，其将传统的三端口级联拓扑转换为双端口双栅极器件，以便于用于分立器件应用的器件测试，建模和封装。 该技术改进了传统双端口单栅极HEMT器件的射频性能，轻微的噪声系数下降。

公开(公告)号：US20070290762A1

公开(公告)日：2007-12-20

申请号：US11446204

申请日：2006-06-05

申请人： Cheng-Kuo Lin ,  Wei-Der Chang ,  Yu-Chi Wang

发明人： Cheng-Kuo Lin ,  Wei-Der Chang ,  Yu-Chi Wang

IPC分类号： H03F3/04

CPC分类号： H03F1/301 ,  H03F1/223 ,  H03F3/19 ,  H03F2200/18 ,  H03F2200/294 ,  H03F2200/451

摘要： A two-port dual-gate field-effect transistor for amplifier applications, wherein a self-bias circuit comprising a number of passive elements, such as resistors, diodes and capacitors, is utilized to coupled the output of the amplifier with a second gate of the dual-gate device as a bias source, which transforms the conventional three-port cascode topology into a two-port dual-gate device so as to facilitate device testing, modeling, and packaging for discrete device application. The technology is for improving the RF performance of conventional two-port single-gate HEMT device, with slightly noise figure degradation. This innovation doesn't require complicated RF testing and modeling as compared with conventional dual-gate devices. The two-port dual-gate device fits packaging molds of conventional two-port discrete device, hence the production line thereof can be easily extended to low noise amplifier and power amplifier applications.

摘要翻译： 一种用于放大器应用的双端口双栅场效应晶体管，其中包括多个无源元件（例如电阻器，二极管和电容器）的自偏置电路用于将放大器的输出与第二栅极 双栅极器件作为偏置源，其将传统的三端口共源共栅拓扑转换为双端口双栅极器件，以便于分立器件应用的器件测试，建模和封装。 该技术用于提高传统双端口单栅极HEMT器件的RF性能，具有轻微的噪声系数下降。 与传统的双栅极器件相比，该创新不需要复杂的RF测试和建模。 双端口双栅极器件适用于传统双端口分立器件的封装模具，因此其生产线可以轻松扩展到低噪声放大器和功率放大器应用。

公开(公告)号：US20080220599A1

公开(公告)日：2008-09-11

申请号：US12153206

申请日：2008-05-15

申请人： Cheng-Kuo Lin ,  Chia-Liang Chao ,  Ming-Chang Tu ,  Tsung-Chi Tsai ,  Yu-Chi Wang

发明人： Cheng-Kuo Lin ,  Chia-Liang Chao ,  Ming-Chang Tu ,  Tsung-Chi Tsai ,  Yu-Chi Wang

IPC分类号： H01L21/28

CPC分类号： H01L29/66462 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/66318 ,  H01L29/7371 ,  H01L29/7785 ,  Y10S438/949 ,  Y10S438/95

摘要： A method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices, particularly for integrated HBT/HEMT devices on a common substrate is disclosed. The method is based on dual-resist processes, wherein a first thin photo-resist layer is utilized for defining the gate dimension, while a second thicker photo-resist layer is used to obtain a better coverage on the surface for facilitating gate metal lift-off. The dual-resist method not only reduces the final gate length, but also mitigates the gate recess undercuts, as compared with those fabricated by the conventional single-resist processes. Furthermore, the dual-resist method of the present invention is also beneficial for the fabrication of multi-gate device with good gate-length uniformity.

摘要翻译： 公开了一种用于集成的III-V化合物半导体器件的短栅极长度电极的方法，特别是用于公共衬底上的集成HBT / HEMT器件的方法。 该方法基于双抗蚀剂工艺，其中使用第一薄的光致抗蚀剂层来限定栅极尺寸，而第二较厚的光致抗蚀剂层用于在表面上获得更好的覆盖以便于栅极金属提升 - 关闭 与通过常规单抗蚀剂工艺制造的那些相比，双重抗蚀剂方法不仅降低了最终栅极长度，而且减小了栅极凹槽底切。 此外，本发明的双电阻法也有利于制造栅极长度均匀性好的多栅极器件。

公开(公告)号：US07842591B2

公开(公告)日：2010-11-30

申请号：US12153206

申请日：2008-05-15

申请人： Cheng-Kuo Lin ,  Chia-Liang Chao ,  Ming-Chang Tu ,  Tsung-Chi Tsai ,  Yu-Chi Wang

发明人： Cheng-Kuo Lin ,  Chia-Liang Chao ,  Ming-Chang Tu ,  Tsung-Chi Tsai ,  Yu-Chi Wang

IPC分类号： H01L21/28

CPC分类号： H01L29/66462 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/66318 ,  H01L29/7371 ,  H01L29/7785 ,  Y10S438/949 ,  Y10S438/95

摘要： A method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices, particularly for integrated HBT/HEMT devices on a common substrate is disclosed. The method is based on dual-resist processes, wherein a first thin photo-resist layer is utilized for defining the gate dimension, while a second thicker photo-resist layer is used to obtain a better coverage on the surface for facilitating gate metal lift-off. The dual-resist method not only reduces the final gate length, but also mitigates the gate recess undercuts, as compared with those fabricated by the conventional single-resist processes. Furthermore, the dual-resist method of the present invention is also beneficial for the fabrication of multi-gate device with good gate-length uniformity.

摘要翻译： 公开了一种用于集成的III-V化合物半导体器件的短栅极长度电极的方法，特别是用于公共衬底上的集成HBT / HEMT器件的方法。 该方法基于双抗蚀剂工艺，其中使用第一薄的光致抗蚀剂层来限定栅极尺寸，而第二较厚的光致抗蚀剂层用于在表面上获得更好的覆盖以便于栅极金属提升 - 关闭 与通过常规单抗蚀剂工艺制造的那些相比，双重抗蚀剂方法不仅降低了最终栅极长度，而且减小了栅极凹槽底切。 此外，本发明的双电阻法也有利于制造栅极长度均匀性好的多栅极器件。

公开(公告)号：US20080080108A1

公开(公告)日：2008-04-03

申请号：US11540974

申请日：2006-10-02

申请人： Cheng-Kuo Lin ,  Yu-Chi Wang ,  Joseph Liu ,  Jean Sun

发明人： Cheng-Kuo Lin ,  Yu-Chi Wang ,  Joseph Liu ,  Jean Sun

IPC分类号： H02H9/00

CPC分类号： H01L27/0285

摘要： An on-chip circuit for protection against electrostatic discharge (ESD) is disclosed. Unlike conventional ESD protection circuit using high turn-on voltage diode string, the circuit uses a plural of enhancement-mode HEMT/MESFET triggered by a shorter diode string to shunt large ESD current for protected susceptive RF circuit. Further, by using dual-gate technology of enhancement-mode HEMT/MESFET, the on-chip ESD protection circuit has the less parasitic capacitance without expanding device size for vulnerable RF circuit.

摘要翻译： 公开了一种用于防止静电放电（ESD）的片上电路。 与使用高导通电压二极管串的常规ESD保护电路不同，该电路使用由较短二极管串触发的多个增强型HEMT / MESFET来分流用于保护的感应RF电路的大ESD电流。 此外，通过使用增强型HEMT / MESFET的双栅极技术，片上ESD保护电路具有较小的寄生电容，而不会对易受攻击的RF电路扩大器件尺寸。

公开(公告)号：US07679870B2

公开(公告)日：2010-03-16

申请号：US11540974

申请日：2006-10-02

申请人： Cheng-Kuo Lin ,  Yu-Chi Wang ,  Joseph Liu ,  Jean Sun

发明人： Cheng-Kuo Lin ,  Yu-Chi Wang ,  Joseph Liu ,  Jean Sun

IPC分类号： H02H9/00

CPC分类号： H01L27/0285

摘要： An on-chip circuit for protection against electrostatic discharge (ESD) is disclosed. Unlike conventional ESD protection circuit using high turn-on voltage diode string, the circuit uses a plural of enhancement-mode HEMT/MESFET triggered by a shorter diode string to shunt large ESD current for protected susceptive RF circuit. Further, by using dual-gate technology of enhancement-mode HEMT/MESFET, the on-chip ESD protection circuit has the less parasitic capacitance without expanding device size for vulnerable RF circuit.

摘要翻译： 公开了一种用于防止静电放电（ESD）的片上电路。 与使用高导通电压二极管串的常规ESD保护电路不同，该电路使用由较短二极管串触发的多个增强型HEMT / MESFET来分流用于保护的感应RF电路的大ESD电流。 此外，通过使用增强型HEMT / MESFET的双栅极技术，片上ESD保护电路具有较小的寄生电容，而不会对易受攻击的RF电路扩大器件尺寸。