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公开(公告)号：US20230165091A1
公开(公告)日：2023-05-25
申请号：US17629772
申请日：2021-04-30
发明人： Yuanjie XU , Benlian WANG , Lili DU , Zhenhua ZHANG , Yuxin ZHANG , Pan XU
IPC分类号： H10K59/131 , G09G3/3233 , H10K59/12
CPC分类号： H10K59/1315 , G09G3/3233 , H10K59/1201 , G09G2300/0842 , G09G2300/0819 , G09G2300/0861 , G09G2310/08 , G09G2300/0426 , H10K59/35
摘要： Provided are a display substrate, a preparation method thereof, and a display device. The display substrate includes a display region and a bonding region on one side of the display region. The bonding region at least includes a lead area; the display region includes a plurality of data lines and a plurality of data fanout lines, the lead area includes a plurality of lead wires, and orthographic projections of the plurality of data lines and the plurality of data fanout lines on a plane of the display substrate are at least partially overlapped. At least one lead wire is connected to the data line through the data fanout line. In the lead area, an orthographic projection of any one of the lead wires on the plane of the display substrate and orthographic projections of other lead wires on the plane of the display substrate have no overlap region.
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公开(公告)号：US20230157099A1
公开(公告)日：2023-05-18
申请号：US17627808
申请日：2021-04-30
发明人： Lili DU , Yuanjie XU , Qiwei WANG , Benlian WANG , Yudiao CHENG , Pan XU
IPC分类号： H10K59/131 , H10K59/12
CPC分类号： H10K59/131 , H10K59/1201 , H10K59/35
摘要： Disclosed are a display substrate, a preparation method thereof, and a display device. The display substrate includes a display region and a bonding region on one side of the display region. The bonding region at least includes a lead area. The display region includes a plurality of data lines and a plurality of data fanout lines. The lead area includes a plurality of lead wires. Orthographic projections of the plurality of data lines and the plurality of data fanout lines on a plane of the display substrate are at least partially overlapped. A first end of at least one data fanout line is connected to the lead wire, and a second end of the at least one data fanout line extends in a direction away from the lead area, to be connected to the data line.
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公开(公告)号：US20240212622A1
公开(公告)日：2024-06-27
申请号：US17794994
申请日：2021-08-24
发明人： Pan XU , Hongli WANG , Danyang MA , Guoying WANG , Xing ZHANG , Chengyuan LUO , Ying HAN
IPC分类号： G09G3/3266
CPC分类号： G09G3/3266
摘要： A display substrate includes an underlayer substrate and a circuit structure layer. The circuit structure layer is located in a display area of the underlayer substrate. The circuit structure layer includes at least one first circuit area and at least one second circuit area. The first circuit area includes at least one first gate drive circuit; the second circuit area includes at least one second gate drive circuit. The first gate drive circuit is cascaded with the second gate drive circuit. The first gate drive circuit includes a plurality of cascaded first gate drive units, and the second gate drive circuit includes a plurality of cascaded second gate drive units. A plurality of first gate drive units are sequentially arranged in a second direction, and a plurality of second gate drive units are sequentially arranged in the second direction.
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公开(公告)号：US20240169928A1
公开(公告)日：2024-05-23
申请号：US18421549
申请日：2024-01-24
发明人： Ying HAN , Xuehuan FENG , Yicheng LIN , Pan XU , Guoying WANG , Xing ZHANG , Zhan GAO , Mingi CHU
IPC分类号： G09G3/3266 , G09G3/3275 , G11C19/28 , H01L27/12 , H10K59/121 , H10K59/131
CPC分类号： G09G3/3266 , G09G3/3275 , G11C19/28 , H01L27/124 , H10K59/1213 , H10K59/1216 , H10K59/1315 , G09G2300/0842 , G09G2310/0278 , G09G2310/0286 , G09G2310/061 , G09G2320/0233
摘要： A display panel includes: a substrate, sub-pixels and a gate drive circuit. The sub-pixel includes a pixel drive circuit. The gate drive circuit includes cascaded shift registers, and a shift register is electrically connected to pixel drive circuits in a row of sub-pixels. The gate drive circuit further includes cascade input signal lines and cascade display reset signal lines. The cascade input signal line is configured to connect a shift signal terminal and an input signal terminal of two different shift register; and the cascade display reset signal line is configured to connect a shift signal terminal and a display reset signal terminal of two different shift register. The display panel has sub-pixel regions for arranging the sub-pixels and first gap regions each located between two adjacent columns of sub-pixel regions; the cascade display reset signal lines and the cascade input signal lines are disposed in different first gap regions.
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5.发明公开公开(公告)号：US20240114728A1
公开(公告)日：2024-04-04
申请号：US18538138
申请日：2023-12-13
发明人： Guoying WANG , Zhen SONG , Yicheng LIN , Xing ZHANG , Pan XU , Ling WANG , Ying HAN
IPC分类号： H10K59/122 , H10K59/121 , H10K59/124 , H10K71/00
CPC分类号： H10K59/122 , H10K59/121 , H10K59/124 , H10K71/00 , H10K59/1201
摘要： An organic light-emitting diode (OLED) display substrate, a manufacturing method thereof and a display panel are provided. The OLED display substrate has pixel regions and includes a base substrate and a pixel defining layer disposed on the base substrate; in regions of the pixel defining layer corresponding to the pixel regions, accommodation parts penetrating the pixel defining layer are disposed, and the pixel defining layer is further provided with guide parts disposed corresponding to the accommodation parts, the guide parts are located on a periphery of the corresponding accommodation parts and formed by recessed areas which are formed on a side of the pixel defining layer away from the base substrate, the recessed areas do not penetrate the pixel defining layer, and an orthographic projection of the guide part on the base substrate is directly coupled to an orthographic projection of the corresponding accommodation part on the base substrate.
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公开(公告)号：US20230343812A1
公开(公告)日：2023-10-26
申请号：US17921077
申请日：2021-05-08
发明人： Xing ZHANG , Yicheng LIN , Pan XU , Ying HAN , Guoying WANG , Zhan GAO
IPC分类号： H01L27/15
CPC分类号： H01L27/156
摘要： A display substrate and a display apparatus. Each pixel repeat unit (10) includes two pixel regions (P1, P2) arranged in a first direction, and a light transmission region (T) located between the two pixel regions (P1, P2), where each of the pixel regions (P1, P2) is provided with at least three sub-pixels (A, B, C) which are adjacently provided; and the area of the light transmission region (T) is equal to twice the area of a light transmission region (T) corresponding to a single pixel region (P1, P2).
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公开(公告)号：US20220122533A1
公开(公告)日：2022-04-21
申请号：US17271914
申请日：2020-05-13
发明人： Can YUAN , Pan XU , Yongqian LI , Zhidong YUAN
IPC分类号： G09G3/3233
摘要： Pixel driving method for driving pixel unit display driving method and display substrate are provided. The pixel unit includes pixel driving circuit, including driving transistor, storage capacitor, and data writing circuit, the driving transistor has control electrode coupled to first terminals of the data writing circuit and the storage capacitor, and first electrode coupled to second terminal of the storage capacitor, and second terminal of the data writing circuit is coupled to data line. The pixel driving method includes: loading a data voltage into the data line, and controlling the first and second terminals of the data writing circuit to be connected; controlling the data line to be floating, and maintaining connection between the first and second terminals of the data writing circuit to reduce gate-source voltage of the driving transistor; and controlling the first and second terminals of the data writing circuit to be disconnected.
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8.发明申请公开(公告)号：US20210343973A1
公开(公告)日：2021-11-04
申请号：US17279771
申请日：2020-06-02
发明人： Xing ZHANG , Wei QUAN , Yicheng LIN , Pan XU , Ling WANG , Guoying WANG , Ying HAN , Zhan GAO
摘要： The present disclosure provides a display substrate, including: a base substrate, which includes a display region and a driving region arranged on at least one side of the display region; a first electrode layer disposed in the display region; a signal output part disposed in the driving region, the first electrode layer is electrically coupled to the signal output part, the first electrode layer comprises a plurality of electrode regions each having a same area; and a plurality of auxiliary electrodes, which are in one-to-one correspondence with the plurality of electrode regions and configured to be coupled in parallel with the first electrode layer, a resistance of each auxiliary electrode is inversely correlated with a minimum distance from the electrode region corresponding to said each auxiliary electrode to the signal output part. The present disclosure further provides a display panel and a manufacturing method thereof and a display device.
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公开(公告)号：US20210335278A1
公开(公告)日：2021-10-28
申请号：US16329352
申请日：2018-08-24
发明人： Danna SONG , Yi Cheng LIN , Pan XU , Zhongyuan WU
IPC分类号： G09G3/3291 , G09G3/3258 , G09G3/00
摘要： A detection method of a pixel circuit, a driving method of a display panel, and a display device are disclosed. The pixel circuit includes a driving transistor; and the detection method of the pixel circuit includes: in the first charge cycle, applying a first data voltage to a gate electrode of the driving transistor, acquiring a first sensing voltage at a first electrode of the driving transistor within the first duration after the application of the first data voltage and before the driving transistor is switched off, and determining whether the first sensing voltage is equal to reference sensing voltage.
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公开(公告)号：US20210335269A1
公开(公告)日：2021-10-28
申请号：US17206121
申请日：2021-03-19
发明人： Zhidong YUAN , Pan XU , Yongqian LI , Can YUAN
IPC分类号： G09G3/3266 , G09G3/3233 , G11C19/28
摘要： The present disclosure relates to the field of display technology, and provides a shift register unit and a driving method thereof, a gate driving circuit, and a display panel. The shift register unit includes: an input circuit, a charging circuit, an inverter circuit, an output circuit, and a pull-down circuit. The input circuit is connected to a second clock signal terminal, a signal input terminal and a first node. The inverter circuit is connected to the signal input terminal, the second clock signal terminal, a first power supply terminal, a second power supply terminal and a pull-down node. The output circuit is connected to the pull-up node, the first power supply terminal and an output terminal. The pull-down circuit is connected to the pull-down node, the second power supply terminal, the pull-up node, and the output terminal.
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