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    PERFORMANCE SCALING DEVICE, PROCESSOR HAVING THE SAME, AND PERFORMANCE SCALING METHOD THEREOF
    1.
    发明申请
    PERFORMANCE SCALING DEVICE, PROCESSOR HAVING THE SAME, AND PERFORMANCE SCALING METHOD THEREOF 有权
    性能调整装置，具有该功能的处理器及其性能调整方法

    公开(公告)号：US20110314306A1

    公开(公告)日：2011-12-22

    申请号：US12881190

    申请日：2010-09-14

    申请人： Chi-Hung Lin ,  Pi-Cheng Hsiao ,  Tay-Jyi Lin ,  Gin-Kou Ma

    发明人： Chi-Hung Lin ,  Pi-Cheng Hsiao ,  Tay-Jyi Lin ,  Gin-Kou Ma

    IPC分类号： G06F1/26

    CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    摘要： A performance scaling device, a processor having the same, and a performance scaling method thereof are provided. The performance scaling device includes an adaptive voltage scaling unit, a latency prediction unit, and a variable-latency datapath. The adaptive voltage scaling unit generates a plurality of operation voltages and transmits the operation voltages to the variable-latency datapath. The variable-latency datapath operates with different latencies according to the operation voltages and generates an operation latency. The latency prediction unit receives the operation latency and a system latency tolerance and generates a voltage scaling signal for the adaptive voltage scaling unit according to the operation latency and the system latency tolerance. The adaptive voltage scaling unit outputs and scales the operation voltages thereof according to the voltage scaling signal.

    摘要翻译： 提供了一种性能缩放装置，具有该性能缩放装置的处理器及其性能缩放方法。 性能缩放装置包括自适应电压缩放单元，等待时间预测单元和可变延迟数据路径。 自适应电压缩放单元产生多个操作电压并将操作电压发送到可变延迟数据路径。 可变延迟数据路径根据操作电压运行不同的延迟，并产生运行延迟。 延迟预测单元接收操作等待时间和系统等待时间容差，并且根据操作等待时间和系统等待时间容差产生用于自适应电压缩放单元的电压缩放信号。 自适应电压调整单元根据电压缩放信号输出并缩放其工作电压。

    Performance scaling device, processor having the same, and performance scaling method thereof
    2.
    发明授权
    Performance scaling device, processor having the same, and performance scaling method thereof 有权
    性能缩放设备，具有相同性能的处理器及其性能缩放方法

    公开(公告)号：US08589718B2

    公开(公告)日：2013-11-19

    申请号：US12881190

    申请日：2010-09-14

    申请人： Chi-Hung Lin ,  Pi-Cheng Hsiao ,  Tay-Jyi Lin ,  Gin-Kou Ma

    发明人： Chi-Hung Lin ,  Pi-Cheng Hsiao ,  Tay-Jyi Lin ,  Gin-Kou Ma

    IPC分类号： G06F1/00

    CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    摘要： A performance scaling device, a processor having the same, and a performance scaling method thereof are provided. The performance scaling device includes an adaptive voltage scaling unit, a latency prediction unit, and a variable-latency datapath. The adaptive voltage scaling unit generates a plurality of operation voltages and transmits the operation voltages to the variable-latency datapath. The variable-latency datapath operates with different latencies according to the operation voltages and generates an operation latency. The latency prediction unit receives the operation latency and a system latency tolerance and generates a voltage scaling signal for the adaptive voltage scaling unit according to the operation latency and the system latency tolerance. The adaptive voltage scaling unit outputs and scales the operation voltages thereof according to the voltage scaling signal.

    摘要翻译： 提供了一种性能缩放装置，具有该性能缩放装置的处理器及其性能缩放方法。 性能缩放装置包括自适应电压缩放单元，等待时间预测单元和可变延迟数据路径。 自适应电压缩放单元产生多个操作电压并将操作电压发送到可变延迟数据路径。 可变延迟数据路径根据操作电压运行不同的延迟，并产生运行延迟。 延迟预测单元接收操作等待时间和系统等待时间容差，并且根据操作等待时间和系统等待时间容差产生用于自适应电压缩放单元的电压缩放信号。 自适应电压调整单元根据电压缩放信号输出并缩放其工作电压。

    Processing device for determining whether to output a first data using a first clock signal or a second data using delay from the first clock signal according to a control signal
    3.
    发明授权
    Processing device for determining whether to output a first data using a first clock signal or a second data using delay from the first clock signal according to a control signal 有权
    处理装置，用于根据控制信号确定是否使用第一时钟信号或第二数据使用延迟从第一时钟信号输出第一数据

    公开(公告)号：US08499188B2

    公开(公告)日：2013-07-30

    申请号：US12890110

    申请日：2010-09-24

    申请人： Chou-Kun Lin ,  Tay-Jyi Lin ,  Pi-Cheng Hsiao ,  Yuan-Hua Chu

    发明人： Chou-Kun Lin ,  Tay-Jyi Lin ,  Pi-Cheng Hsiao ,  Yuan-Hua Chu

    IPC分类号： G06F1/04 ,  G06F1/00

    CPC分类号： G06F1/10

    摘要： An embodiment of a processing device includes a function unit and a control unit. The function unit receives input data and performs a specific operation to the input data to generate result data. The control unit receives the result data and generates an output signal. The control unit latches the result data according to a first clock signal to generate first data and latches the result data according to a second clock signal to generate second data. The control unit compares the first data with the second data to generate a control signal and selects the first data or the second data to serve as data of the output signal according to the control signal. The second clock signal is delayed from the first clock signal by a predefined time period.

    摘要翻译： 处理装置的实施例包括功能单元和控制单元。 功能单元接收输入数据并对输入数据执行特定操作以产生结果数据。 控制单元接收结果数据并产生输出信号。 控制单元根据第一时钟信号锁存结果数据，以产生第一数据，并根据第二时钟信号锁存结果数据，以产生第二数据。 控制单元将第一数据与第二数据进行比较以产生控制信号，并根据控制信号选择第一数据或第二数据作为输出信号的数据。 第二时钟信号从第一时钟信号延迟预定时间段。

    Method for inter-cluster communication that employs register permutation
    5.
    发明申请
    Method for inter-cluster communication that employs register permutation 审中-公开
    采用寄存器排列的集群间通信方法

    公开(公告)号：US20050204118A1

    公开(公告)日：2005-09-15

    申请号：US10787211

    申请日：2004-02-27

    申请人： Chein-Wei Jen ,  Tay-Jyi Lin ,  Chen-Chia Lee ,  Chin-Chi Chang ,  Chih-Wei Liu

    发明人： Chein-Wei Jen ,  Tay-Jyi Lin ,  Chen-Chia Lee ,  Chin-Chi Chang ,  Chih-Wei Liu

    IPC分类号： G06F15/00

    CPC分类号： G06F9/30032 ,  G06F9/3012 ,  G06F9/3828 ,  G06F9/3891

    摘要： The present invention is a method for inter-cluster communication that employs register permutation by dynamically mapping the registers to the functional units. Because only the mapping between registers and functional units is changed and no actual data movement occurs, the present invention greatly diminishes the power consumption. Owing to the inter-cluster communication mechanism, a centralized register file can be replaced with small register sub-blocks, where the silicon area is greatly reduced, and the access time and the power consumption are also diminished.

    摘要翻译： 本发明是一种群间通信的方法，其通过将寄存器动态映射到功能单元来采用寄存器置换。 因为只有寄存器和功能单元之间的映射被改变并且没有发生实际的数据移动，所以本发明大大地降低了功耗。 由于集群间通信机制，集中式寄存器文件可以用小的寄存器子块代替，其中硅面积大大减少，访问时间和功耗也减少。

    Dynamically reconfigurable stages pipelined datapath with data valid signal controlled multiplexer
    6.
    发明授权
    Dynamically reconfigurable stages pipelined datapath with data valid signal controlled multiplexer 有权
    动态可重构级流水线数据通路与数据有效信号控制多路复用器

    公开(公告)号：US07406588B2

    公开(公告)日：2008-07-29

    申请号：US11229616

    申请日：2005-09-20

    申请人： Tay-Jyi Lin ,  Chein-Wei Jen ,  Chih-Wei Liu ,  Po-Han Huang ,  Wei-Sheng Huang ,  Chan-Hao Chang

    发明人： Tay-Jyi Lin ,  Chein-Wei Jen ,  Chih-Wei Liu ,  Po-Han Huang ,  Wei-Sheng Huang ,  Chan-Hao Chang

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3869

    摘要： A pipelined datapath with dynamically reconfigurable pipeline stages is provided, having a pipeline controller which generates clock signals and selects signals based on a system clock and a valid data signal to control each of the registers and each of the multiplexers in the pipeline circuit. In other words, when a valid datum is being processed, the pipeline register is activated to latch the output of the combinational logic circuit; otherwise, when an invalid datum is received, the register is not activated and the datum bypasses the register through a multiplexer. Therefore, the pipeline stages of the pipelined datapath are dynamically reconfigured to save the power dissipation effectively.

    摘要翻译： 提供了具有动态可重构流水线级的流水线数据路径，具有管线控制器，其生成时钟信号并基于系统时钟和有效数据信号选择信号，以控制流水线电路中的每个寄存器和多路复用器。 换句话说，当正在处理有效数据时，激活流水线寄存器来锁存组合逻辑电路的输出; 否则，当接收到无效数据时，寄存器不被激活，并且基准通过多路复用器旁路寄存器。 因此，流水线数据路径的流水线级可动态重新配置，有效节省功耗。

    Pipelined datapath with dynamically reconfigurable pipeline stages
    7.
    发明申请
    Pipelined datapath with dynamically reconfigurable pipeline stages 有权
    具有动态可重构流水线阶段的流水线数据路径

    公开(公告)号：US20060259748A1

    公开(公告)日：2006-11-16

    申请号：US11229616

    申请日：2005-09-20

    申请人： Tay-Jyi Lin ,  Chein-Wei Jen ,  Chih-Wei Liu ,  Po-Han Huang ,  Wei-Sheng Huang ,  Chan-Hao Chang

    发明人： Tay-Jyi Lin ,  Chein-Wei Jen ,  Chih-Wei Liu ,  Po-Han Huang ,  Wei-Sheng Huang ,  Chan-Hao Chang

    IPC分类号： G06F9/44

    CPC分类号： G06F9/3869

    摘要： A pipelined datapath with dynamically reconfigurable pipeline stages is provided, having a pipeline controller which generates clock signals and selects signals based on a system clock and a valid data signal to control each of the registers and each of the multiplexers in the pipeline circuit. In other words, when a valid datum is being processed, the pipeline register is activated to latch the output of the combinational logic circuit; otherwise, when an invalid datum is received, the register is not activated and the datum bypasses the register through a multiplexer. Therefore, the pipeline stages of the pipelined datapath are dynamically reconfigured to save the power dissipation effectively.

    摘要翻译： 提供了具有动态可重构流水线级的流水线数据路径，具有管线控制器，其生成时钟信号并基于系统时钟和有效数据信号选择信号，以控制流水线电路中的每个寄存器和多路复用器。 换句话说，当正在处理有效数据时，激活流水线寄存器来锁存组合逻辑电路的输出; 否则，当接收到无效数据时，寄存器不被激活，并且基准通过多路复用器旁路寄存器。 因此，流水线数据路径的流水线级可动态重新配置，有效节省功耗。

    Inter-cluster communication module using the memory access network
    8.
    发明申请
    Inter-cluster communication module using the memory access network 有权
    群集间通信模块使用内存接入网

    公开(公告)号：US20060212663A1

    公开(公告)日：2006-09-21

    申请号：US11246115

    申请日：2005-10-11

    申请人： Tay-Jyi Lin ,  Pi-Chen Hsiao ,  Chih-Wei Liu ,  Chein-Wei Jen ,  I-Tao Liao ,  Po-Han Huang

    发明人： Tay-Jyi Lin ,  Pi-Chen Hsiao ,  Chih-Wei Liu ,  Chein-Wei Jen ,  I-Tao Liao ,  Po-Han Huang

    IPC分类号： G06F12/00

    CPC分类号： G06F15/173

    摘要： An inter-cluster communication module using the memory access network is provided, including a plurality of clusters, a memory subsystem, a controller and a switch device. When some clusters issue a load instruction and some clusters issue a store instruction of an identical memory address concurrently, the controller controls the switch device which connects the clusters and the memory banks of the memory subsystem, so that the data item is transmitted from the cluster issuing the store instruction to the cluster issuing the load instruction through the switch device, thereby achieving data exchange between the clusters. Herein, the data item is selectively stored in the memory module depending on the address. Furthermore, the data item is also transmitted between the memory and the clusters over the switch device.

    摘要翻译： 提供了使用存储器访问网络的集群间通信模块，包括多个集群，存储器子系统，控制器和交换设备。 当一些集群发出加载指令并且一些集群同时发出相同存储器地址的存储指令时，控制器控制连接存储器子系统的集群和存储器组的交换设备，从而从集群发送数据项 通过交换设备向发布加载指令的集群发出存储指令，由此实现集群之间的数据交换。 这里，数据项根据地址被选择性地存储在存储器模块中。 此外，数据项也通过交换设备在存储器和簇之间传输。

    Virtual Cluster Architecture And Method
    9.
    发明申请
    Virtual Cluster Architecture And Method 审中-公开
    虚拟集群架构与方法

    公开(公告)号：US20080162870A1

    公开(公告)日：2008-07-03

    申请号：US11780480

    申请日：2007-07-20

    申请人： Tay-Jyi Lin ,  Chein-Wei Jen ,  Pi-Chen Hsiao ,  Li-Chun Lin ,  Chih-Wei Liu

    发明人： Tay-Jyi Lin ,  Chein-Wei Jen ,  Pi-Chen Hsiao ,  Li-Chun Lin ,  Chih-Wei Liu

    IPC分类号： G06F15/00

    CPC分类号： G06F9/3824 ,  G06F9/3828 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3891

    摘要： Disclosed is a virtual cluster architecture and method. The virtual cluster architecture includes N virtual clusters, N register files, M sets of function units, a virtual cluster control switch, and an inter-cluster communication mechanism. This invention uses a way of time sharing or time multiplexing to alternatively execute a single program thread across multiple parallel clusters. It minimizes the hardware resources for complicated forwarding circuitry or bypassing mechanism by greatly increasing the tolerance of instruction latency in the datapath. This invention may distribute function units serially into pipeline stages to support composite instructions. The performance and the code sizes of application programs can therefore be significantly improved with these composite instructions, of which the introduced latency can be completely hidden in this invention. This invention also has the advantage of being compatible with the program codes developed on conventional multi-cluster architectures.

    摘要翻译： 公开了一种虚拟集群架构和方法。 虚拟集群架构包括N个虚拟集群，N个寄存器文件，M个功能单元组，一个虚拟集群控制交换机和一个集群间通信机制。 本发明使用时间共享或时间复用的方式来交替地在多个并行簇上执行单个程序线程。 它通过大大增加数据路径中指令延迟的容限，最大限度地减少了复杂转发电路或旁路机制的硬件资源。 本发明可以将功能单元串行地分配到流水线阶段以支持复合指令。 因此，通过这些复合指令可以显着改善应用程序的性能和代码大小，其中引入的延迟可以完全隐藏在本发明中。 本发明还具有与常规多集群架构上开发的程序代码兼容的优点。