公开(公告)号：US5753418A

公开(公告)日：1998-05-19

申请号：US706876

申请日：1996-09-03

申请人： Chia Shiung Tsai ,  Yuan-Chang Huang ,  Chen-Hua Yu

发明人： Chia Shiung Tsai ,  Yuan-Chang Huang ,  Chen-Hua Yu

IPC分类号： G03F7/09 ,  H01L21/027 ,  H01L21/311 ,  G03F7/00

CPC分类号： H01L21/31144 ,  G03F7/091 ,  H01L21/0276 ,  H01L21/31138

摘要： A method for forming a patterned layer within an integrated circuit. There is first provided a substrate having formed thereover a blanket target layer. There is then formed upon the blanket target layer a blanket focusing layer, where the blanket focusing layer is formed of an organic anti-reflective coating (ARC) material which is susceptible to a reproducible positive taper within a first etch method employed in forming from the blanket focusing layer a patterned focusing layer. The first etch method is a first plasma etch method employing an etchant gas composition comprising carbon tetrafluoride and argon. There is then formed upon the blanket focusing layer a blanket photoresist layer. The blanket photoresist layer is then photoexposed and developed layer to form a patterned photoresist layer. The blanket focusing layer is then etched through the first etch method to form the patterned focusing layer while employing the patterned photoresist layer as a first etch mask layer, where the patterned focusing layer has the reproducible positive taper with respect to the patterned photoresist layer and the blanket target layer. Finally, the blanket target layer is etched through a second etch method to form a patterned target layer while employing the patterned focusing layer as a second etch mask layer, where the patterned target layer has a reproducible second etch bias with respect to the patterned focusing layer, where the reproducible second etch bias does not substantially compensate the reproducible positive taper, and where the width of an aperture within the patterned target layer varies inversely as a function of the thickness of the patterned focusing layer.

摘要翻译： 一种用于在集成电路内形成图案层的方法。 首先提供了在覆盖目标层之上形成的衬底。 然后在毯子目标层上形成橡皮布聚焦层，其中橡皮布聚焦层由有机抗反射涂层（ARC）材料形成，该有机抗反射涂层（ARC）材料在第一蚀刻方法中易于产生可再现的正锥度， 毯状聚焦层是图案化聚焦层。 第一蚀刻方法是使用包含四氟化碳和氩的蚀刻剂气体组合物的第一等离子体蚀刻方法。 然后在橡皮布聚焦层上形成覆盖光致抗蚀剂层。 然后将覆盖的光致抗蚀剂层照相和显影，以形成图案化的光致抗蚀剂层。 然后通过第一蚀刻方法蚀刻橡皮布聚焦层以形成图案化聚焦层，同时使用图案化的光致抗蚀剂层作为第一蚀刻掩模层，其中图案化的聚光层相对于图案化的光致抗蚀剂层具有可再现的正锥度， 毯子目标层。 最后，通过第二蚀刻方法蚀刻覆盖层目标层以形成图案化目标层，同时使用图案化聚焦层作为第二蚀刻掩模层，其中图案化目标层相对于图案化聚光层具有可再现的第二蚀刻偏置 ，其中可再现的第二蚀刻偏压基本上不补偿可再现的正锥度，并且其中图案化目标层内的孔的宽度作为图案化聚焦层的厚度的函数反向变化。

公开(公告)号：US5858621A

公开(公告)日：1999-01-12

申请号：US788874

申请日：1997-01-22

申请人： Chen-hua Yu ,  Chia Shiung Tsai

发明人： Chen-hua Yu ,  Chia Shiung Tsai

IPC分类号： G03F7/09 ,  G03F7/26 ,  G03C5/00

CPC分类号： G03F7/094 ,  G03F7/265

摘要： A novel bi-layer using a silylation process and anti-reflective coatings are employed for making distortion-free submicrometer photoresist patterns. The method involves forming a multilayer composed of a bottom anti-reflective coating (BARC), a first photoresist layer, a middle anti-reflective coating (MARC), and a silylated second photoresist layer for patterning an underlying electrically conducting layer, such as for FET gate electrodes. The upper photoresist layer is then optically exposed through a mask to form a latent image, and is silylated selectively to form a silicon rich region. The BARC and MARC layers prevent reflected radiation from the underlying structure during the optical exposure, thereby providing a distortion-free latent image. The selective silylation of the latent image portion of the photoresist serves as an excellent etch mask for oxygen plasma etching which is then used to pattern the remaining photoresist layer and anti-reflective coatings. The resulting distortion-free photoresist pattern is then used as an etch mask for etching the underlying electrically conducting layer.

摘要翻译： 采用了使用甲硅烷化方法和抗反射涂层的新型双层，用于制造无变形亚微米光刻胶图案。 该方法包括形成由底部抗反射涂层（BARC），第一光致抗蚀剂层，中间抗反射涂层（MARC）和用于图案化下面的导电层的甲硅烷基化第二光致抗蚀剂层（例如， FET栅电极。 然后通过掩模将上光致抗蚀剂层光学曝光以形成潜像，并被选择性地甲硅烷基化以形成富含硅的区域。 BARC和MARC层在光学曝光期间防止来自底层结构的反射辐射，从而提供无失真的潜像。 光致抗蚀剂的潜像部分的选择性甲硅烷基化用作氧等离子体蚀刻的优良蚀刻掩模，然后用于对剩余的光致抗蚀剂层和抗反射涂层进行图案化。 然后将所得到的无失真光致抗蚀剂图案用作蚀刻掩模以蚀刻下面的导电层。

公开(公告)号：US5871658A

公开(公告)日：1999-02-16

申请号：US782708

申请日：1997-01-13

申请人： Hun-Jan Tao ,  Chia Shiung Tsai ,  Chen-Hua Yu

发明人： Hun-Jan Tao ,  Chia Shiung Tsai ,  Chen-Hua Yu

IPC分类号： H01L21/66 ,  H01L21/00

CPC分类号： B24B37/013 ,  H01L22/26

摘要： A method for monitoring and controlling a plasma etch method for forming a patterned layer. There is first provided a substrate having a blanket layer formed thereover, the blanket layer having a patterned photoresist layer formed thereupon. There is then etched through a plasma etch method while employing the patterned photoresist layer as a patterned photoresist etch mask layer the blanket layer to form a patterned layer. The plasma etch method is monitored through an optical emission spectroscopy (OES) method which monitors a minimum of a first plasma etchant component which relates to a chemical etching of the blanket layer and a second plasma etchant component which relates to a physical sputter etching of the blanket layer and the patterned photoresist layer. While etching through the plasma etch method there is adjusted at least one of a first control parameter which controls the first plasma etchant component concentration and a second control parameter which controls the second plasma etchant component concentration to provide through the plasma etch method from the blanket layer a patterned layer with a pre-determined blanket layer to patterned photoresist layer plasma etch selectivity. There is also disclosed an apparatus through which the method may be practiced.

摘要翻译： 一种用于监测和控制用于形成图案化层的等离子体蚀刻方法的方法。 首先提供了具有在其上形成的覆盖层的衬底，所述覆盖层具有在其上形成的图案化的光致抗蚀剂层。 然后通过等离子体蚀刻方法蚀刻，同时使用图案化的光致抗蚀剂层作为图案化的光致抗蚀剂蚀刻掩模层来形成图案层。 等离子体蚀刻方法是通过光学发射光谱法（OES）监测的，该方法监测与第一等离子体蚀刻剂成分有关的最小值，该第一等离子体蚀刻剂成分涉及橡皮布层的化学蚀刻和第二等离子体蚀刻剂部件，其涉及物理溅射蚀刻 覆盖层和图案化的光致抗蚀剂层。 在蚀刻通过等离子体蚀刻方法时，调节控制第一等离子体蚀刻剂成分浓度的第一控制参数和控制第二等离子体蚀刻剂成分浓度的第二控制参数中的至少一个，以通过等离子体蚀刻方法从覆盖层 具有预定覆盖层的图案化层到图案化的光致抗蚀剂层等离子体蚀刻选择性。 还公开了可以实施该方法的装置。

公开(公告)号：US5872061A

公开(公告)日：1999-02-16

申请号：US958429

申请日：1997-10-27

申请人： Shing-Long Lee ,  Chia Shiung Tsai ,  So Wein Kuo

发明人： Shing-Long Lee ,  Chia Shiung Tsai ,  So Wein Kuo

IPC分类号： H01L21/311 ,  H01L21/302

CPC分类号： H01L21/02063 ,  H01L21/31116

摘要： A method for forming a patterned fluorine containing plasma etched layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a fluorine containing plasma etchable layer. There is then formed upon the fluorine containing plasma etchable layer a patterned photoresist layer. There is then etched through a fluorine containing plasma etching method while employing the patterned photoresist layer as a photoresist etch mask layer the fluorine containing plasma etchable layer to form a patterned fluorine containing plasma etched layer. The patterned fluorine containing plasma etched layer has a fluoropolymer residue layer formed thereupon. The fluorine containing plasma etch method employs a first etchant gas composition comprising a nitrogen trifluoride etchant gas. Finally, there is stripped through an oxygen containing plasma stripping method the patterned photoresist layer and the fluoropolymer residue layer from the patterned fluorine containing plasma etched layer. The oxygen containing plasma stripping method employs a second etchant gas composition comprising a fluorine containing etchant gas and an oxygen containing etchant gas.

摘要翻译： 一种用于在微电子学制造中形成图案化含氟等离子体蚀刻层的方法。 首先提供了在微电子制造中使用的衬底。 然后在衬底上形成含氟等离子体可蚀刻层。 然后在含氟等离子体可蚀刻层上形成图案化的光致抗蚀剂层。 然后通过含氟等离子体蚀刻方法蚀刻，同时使用图案化的光致抗蚀剂层作为含氟等离子体可蚀刻层的光致抗蚀剂蚀刻掩模层，以形成图案化含氟等离子体蚀刻层。 图案化的含氟等离子体蚀刻层在其上形成有氟聚合物残留层。 含氟等离子体蚀刻方法使用包含三氟化氮蚀刻剂气体的第一蚀刻剂气体组合物。 最后，通过含氧等离子体剥离方法从图案化的含氟等离子体蚀刻层剥离图案化的光致抗蚀剂层和含氟聚合物残余物层。 含氧等离子体汽提方法采用包含含氟蚀刻剂气体和含氧蚀刻剂气体的第二蚀刻剂气体组合物。

公开(公告)号：US5880005A

公开(公告)日：1999-03-09

申请号：US956967

申请日：1997-10-23

申请人： Chia Shiung Tsai ,  Hun-Jan Tao

发明人： Chia Shiung Tsai ,  Hun-Jan Tao

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A method for creating a tapered profile insulator shape, on an underlying silicon nitride layer, using a photoresist shape as a mask, has been developed. A two step dry etching procedure is used, featuring a first dry etching phase, using an etching chemistry comprised of argon, CHF.sub.3 and CF.sub.4, resulting in a tapered profile insulator shape, underlying the photoresist shape. A second dry etching phase, exhibiting high etch rate selectivity between insulator layer and underlying silicon nitride, via use of an etching chemistry comprised of argon, CHF.sub.3, CH.sub.2 F.sub.2, and CH.sub.3 F, is used to remove residual insulator layer from the underlying silicon nitride layer, without significant attack of the underlying silicon nitride layer.

摘要翻译： 已经开发了使用光致抗蚀剂形状作为掩模在下面的氮化硅层上形成锥形轮廓绝缘体形状的方法。 使用两步干蚀刻方法，其特征在于使用由氩，CHF 3和CF 4构成的蚀刻化学品的第一干蚀刻阶段，导致在光致抗蚀剂形状下面的锥形轮廓绝缘体形状。 通过使用由氩，CHF 3，CH 2 F 2和CH 3 F组成的蚀刻化学品，在绝缘体层和下面的氮化硅之间表现出高蚀刻速率选择性的第二干法蚀刻阶段用于从下面的氮化硅层去除残留的绝缘体层， 没有显着攻击下面的氮化硅层。

公开(公告)号：US5728619A

公开(公告)日：1998-03-17

申请号：US618890

申请日：1996-03-20

申请人： Chia Shiung Tsai ,  Chen-Hua Douglas Yu

发明人： Chia Shiung Tsai ,  Chen-Hua Douglas Yu

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/336

CPC分类号： H01L21/31116 ,  H01L21/76816

摘要： A method for forming within an integrated circuit a narrow line-width high aspect ratio via through a first integrated circuit layer which resides upon a second integrated circuit layer. There is first formed upon a semiconductor substrate a second integrated circuit layer which has formed upon its surface a first integrated circuit layer. Through a first etch method, a partial via is then formed within the first integrated circuit layer to a distance of from about 2500 to about 4000 angstroms above the surface of the second integrated circuit layer. The first etch method is chosen to provide a partial via with substantially parallel sidewalls. Through a second etch method, the partial via is then etched completely through the first integrated circuit layer. The second etch method is chosen to possesses an etch selectivity ratio for the first integrated circuit layer with respect to the second integrated circuit layer of at least about 60:1. The method is preferably employed in forming narrow line-width high aspect ratio vias through insulator layers beneath which reside metal silicide layers formed upon integrated circuit device electrodes within integrated circuits.

摘要翻译： 一种在集成电路内通过位于第二集成电路层上的第一集成电路层形成窄线宽高宽比通孔的方法。 首先在半导体衬底上形成第二集成电路层，该第二集成电路层在其表面上形成第一集成电路层。 通过第一蚀刻方法，然后在第一集成电路层内形成部分通孔至第二集成电路层表面之上约2500至约4000埃的距离。 选择第一蚀刻方法以提供具有基本上平行的侧壁的部分通孔。 通过第二蚀刻方法，然后通过第一集成电路层完全蚀刻部分通孔。 第二蚀刻方法被选择为具有相对于第二集成电路层的至少约60:1的第一集成电路层的蚀刻选择率。 该方法优选用于通过绝缘体层形成狭窄的线宽高纵横比通孔，在绝缘层下方在集成电路内的集成电路器件电极上形成金属硅化物层。

公开(公告)号：US07906418B2

公开(公告)日：2011-03-15

申请号：US10727272

申请日：2003-12-03

申请人： Chung-Yi Yu ,  Chi-Hsin Lo ,  Chia Shiung Tsai

发明人： Chung-Yi Yu ,  Chi-Hsin Lo ,  Chia Shiung Tsai

IPC分类号： H01L21/3205

CPC分类号： H01L27/11521 ,  H01L23/485 ,  H01L27/115 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device, wherein a gate structure is formed over a substrate, an interconnect layer is formed over the gate structure and the substrate, and a cap layer is formed over the interconnect layer. The interconnect layer and the cap layer are then planarized to form a substantially planar surface. A mask layer, such as an oxide mask layer, is formed over the planarized portions of the interconnect layer, and the planarized cap layer and portions of the interconnect layer are removed by etching around the mask layer.

摘要翻译： 一种制造半导体器件的方法，其中在衬底上形成栅极结构，在所述栅极结构和所述衬底之上形成互连层，并且在所述互连层上形成覆盖层。 然后将互连层和覆盖层平坦化以形成基本平坦的表面。 在互连层的平坦化部分上形成掩模层，例如氧化物掩模层，并且通过围绕掩模层进行蚀刻来去除平坦化的覆盖层和互连层的部分。

公开(公告)号：US06326296B1

公开(公告)日：2001-12-04

申请号：US09108867

申请日：1998-07-01

申请人： Chia Shiung Tsai ,  Hun-Jan Tao

发明人： Chia Shiung Tsai ,  Hun-Jan Tao

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3185 ,  H01L2221/1036

摘要： A new method of forming a dual damascene interconnect is disclosed for manufacturing semiconductor substrates. A contact/via hole is first formed in a first dielectric layer formed over a substructure of a substrate having devices formed therein and/or metal layers formed thereon. The contact/via hole is filled with a protective material prior to forming a second dielectric layer. Conductive line opening is formed in the second dielectric layer and over the contact/via hole having the protective material in it. The protective material protects the edge of the contact/via hole from damage due to the second etching of the conductive line opening. Thus, a dual damascene structure is disclosed wherein the integrity of the edge of the contact/via hole is preserved, avoiding any reliability problems in the semiconductor product.

摘要翻译： 公开了一种形成双镶嵌互连的新方法，用于制造半导体衬底。 接触/通孔首先形成在形成在其上形成有器件和/或其上形成金属层的衬底的子结构之上的第一电介质层中。 在形成第二电介质层之前，接触/通孔填充有保护材料。 导电线路开口形成在第二电介质层中并且在其中具有保护材料的接触/通孔之上。 保护材料保护接触/通孔的边缘免受由于导电线开口的第二次蚀刻的损害。 因此，公开了一种双镶嵌结构，其中保留了接触/通孔的边缘的完整性，避免了半导体产品中的任何可靠性问题。

公开(公告)号：US06316348B1

公开(公告)日：2001-11-13

申请号：US09838627

申请日：2001-04-20

申请人： Chu Yun Fu ,  Chia Shiung Tsai ,  Syun-Ming Jang

发明人： Chu Yun Fu ,  Chia Shiung Tsai ,  Syun-Ming Jang

IPC分类号： H01L214763

CPC分类号： H01L21/76829 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76813

摘要： The present invention provides an anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer and two compatible oxide etch processes. The Si-Rich Silicon oxynitride (SiON) etch barrier layer can be used as a hard mask in a dual damascene structure and as a hard mask for over a polysilicone gate. The invention has the following key elements: 1) Si rich Silicon oxynitride (SiON) ARC layer, 2) Special Silicon oxide Etch process that has a high selectivity of Si-Rich SiON to silicon oxide or SiN; 3) Special Si Rich SiON spacer process for a self aligned contact (SAC). A dual damascene structure is formed by depositing a first dielectric layer. A novel anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer is deposited on top of the first dielectric layer. A first opening is etched in the first insulating layer. A second dielectric layer is deposited on the anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer. A second dual damascene opening is etched into the dielectric layers. The anti-reflective Si-Rich Silicon oxynnitride (SiON) etch barrier layer can also serve as an ARC layer during these operations to reduce the amount of reflectance from conductive region to reduce distortion of the photoresist pattern.

摘要翻译： 本发明提供了抗反射富Si硅氮化硅（SiON）蚀刻阻挡层和两种相容的氧化物蚀刻工艺。 Si富氧硅氮化物（SiON）蚀刻阻挡层可用作双镶嵌结构中的硬掩模，并且可用作多晶硅栅极上的硬掩模。 本发明具有以下关键要素：1）富硅氧氮化硅（SiON）ARC层，2）具有Si富Si硅对硅氧化物或SiN的高选择性的特殊氧化硅蚀刻工艺; 3）用于自对准接触（SAC）的特殊Si Rich SiON隔离工艺。通过沉积第一介电层形成双镶嵌结构。 在第一介电层的顶部沉积有新的抗反射硅富氮硅氮化硅（SiON）蚀刻阻挡层。 在第一绝缘层中蚀刻第一开口。 第二电介质层沉积在抗反射富Si硅氮化硅（SiON）蚀刻阻挡层上。 第二个双镶嵌开口被蚀刻到电介质层中。 在这些操作期间，抗反射Si富硅氧氮化物（SiON）蚀刻阻挡层也可以用作ARC层，以减少来自导电区域的反射率，以减少光致抗蚀剂图案的变形。

公开(公告)号：US06245669B1

公开(公告)日：2001-06-12

申请号：US09245564

申请日：1999-02-05

申请人： Chu Yun Fu ,  Chia Shiung Tsai ,  Syun-Ming Jang

发明人： Chu Yun Fu ,  Chia Shiung Tsai ,  Syun-Ming Jang

IPC分类号： H01L214763

CPC分类号： H01L21/76829 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76813

摘要： The present invention provides an anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer and two compatible oxide etch processes. The Si-Rich Silicon oxynitride (SiON) etch barrier layer can be used as a hard mask in a dual damascene structure and as a hard mask for over a polysilicon gate. The invention has the following key elements: 1) Si rich Silicon oxynitride (SiON) ARC layer, 2) Special Silicon oxide Etch process that has a high selectivity of Si-Rich SiON to silicon oxide or SiN; 3) Special Si Rich SiON spacer process for a self aligned contact (SAC). A dual damascene structure is formed by depositing a first dielectric layer. A novel anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer is deposited on top of the first dielectric layer. A first opening is etched in the first insulating layer. A second dielectric layer is deposited on the anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer. A second dual damascene opening is etched into the dielectric layers. The anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer can also serve as an ARC layer during these operations to reduce the amount of reflectance from conductive region to reduce distortion of the photoresist pattern.

摘要翻译： 本发明提供了抗反射富Si硅氮化硅（SiON）蚀刻阻挡层和两种相容的氧化物蚀刻工艺。 Si富氧硅氮化物（SiON）蚀刻阻挡层可用作双镶嵌结构中的硬掩模，并可用作多晶硅栅极上的硬掩模。 本发明具有以下关键要素：1）富硅氧氮化硅（SiON）ARC层，2）具有Si富Si硅对硅氧化物或SiN的高选择性的特殊氧化硅蚀刻工艺; 3）用于自对准接触（SAC）的特殊Si Rich SiON隔离工艺。通过沉积第一介电层形成双镶嵌结构。 在第一介电层的顶部沉积有新的抗反射硅富氮硅氮化硅（SiON）蚀刻阻挡层。 在第一绝缘层中蚀刻第一开口。 第二电介质层沉积在抗反射富Si硅氮化硅（SiON）蚀刻阻挡层上。 第二个双镶嵌开口被蚀刻到电介质层中。 在这些操作期间，抗反射硅富氮硅氮化物（SiON）蚀刻阻挡层也可以用作ARC层，以减少来自导电区域的反射率，以减少光致抗蚀剂图案的失真。