公开(公告)号：US20130196481A1

公开(公告)日：2013-08-01

申请号：US13364119

申请日：2012-02-01

Applicant: Chia Ying Lee ,  Chih-Yuan Ting ,  Jyu-Horng Shieh

Inventor： Chia Ying Lee ,  Chih-Yuan Ting ,  Jyu-Horng Shieh

IPC: H01L21/3105 ,  H01L21/76 ,  H01L21/302

CPC classification number: H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76816

Abstract: A method that includes forming a masking element on a semiconductor substrate and overlying a defined space. A first feature and a second feature are each formed on the semiconductor substrate. The space interposes the first and second features and extends from a first end of the first feature to a first end of the second feature. A third feature is then formed adjacent and substantially parallel the first and second features. The third feature extends at least from the first end of the first feature to the first end of the second feature.

Abstract translation: 一种方法，其包括在半导体衬底上形成掩模元件并覆盖在限定的空间上。 第一特征和第二特征各自形成在半导体衬底上。 该空间插入第一和第二特征并且从第一特征的第一端延伸到第二特征的第一端。 然后，第三特征与第一和第二特征相邻并基本上平行。 第三特征至少从第一特征的第一端延伸到第二特征的第一端。

公开(公告)号：USD564334S1

公开(公告)日：2008-03-18

申请号：US29286160

申请日：2007-04-25

Applicant: Chia Ying Lee

Designer： Chia Ying Lee

公开(公告)号：US07854030B2

公开(公告)日：2010-12-21

申请号：US11876791

申请日：2007-10-23

Applicant: Chia Ying Lee ,  Victor Hoernig

Inventor： Chia Ying Lee ,  Victor Hoernig

IPC: A47J47/20

CPC classification number: A47K1/00 ,  A47K10/08

Abstract: A utility tub is provided with a sink area having support surfaces for removably supporting a tray. The tray may hold items that are drying. In addition, the utility tub may be provided with an enlarged area for supporting other items, and various accessories such as a towel rack or towel pegs.

Abstract translation: 公用浴盆设置有具有用于可移除地支撑托盘的支撑表面的水槽区域。 托盘可能会保持干燥的物品。 此外，公用浴缸可以设置有用于支撑其他物品的扩大区域，以及诸如毛巾架或毛巾钉的各种附件。

公开(公告)号：USD556034S1

公开(公告)日：2007-11-27

申请号：US29286152

申请日：2007-04-25

Applicant: Chia Ying Lee

Designer： Chia Ying Lee

公开(公告)号：US08962484B2

公开(公告)日：2015-02-24

申请号：US13328680

申请日：2011-12-16

Applicant: Chia Ying Lee ,  Chih-Yuan Ting ,  Jyu-Horng Shieh ,  Minghsing Tsai ,  Syun-Ming Jang

Inventor： Chia Ying Lee ,  Chih-Yuan Ting ,  Jyu-Horng Shieh ,  Minghsing Tsai ,  Syun-Ming Jang

IPC: H01L21/32 ,  H01L21/311 ,  H01L21/033 ,  H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32

Abstract: The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor substrate. The first layer is patterned to provide a first element, a second element, and a space interposing the first and second elements. Spacer elements are then formed on the sidewalls on the first and second elements of the first layer. Subsequently, the second layer is etched using the spacer elements and the first and second elements as a masking element.

Abstract translation: 本公开提供了一种方法，包括提供半导体衬底并在半导体衬底上形成第一层和第二层。 图案化第一层以提供第一元件，第二元件和插入第一元件和第二元件的空间。 然后在第一层的第一和第二元件的侧壁上形成间隔元件。 随后，使用间隔元件和第一和第二元素作为掩模元件来蚀刻第二层。

公开(公告)号：USD580185S1

公开(公告)日：2008-11-11

申请号：US29303785

申请日：2008-02-18

Applicant: Chia Ying Lee

Designer： Chia Ying Lee

公开(公告)号：USD578780S1

公开(公告)日：2008-10-21

申请号：US29303783

申请日：2008-02-18

Applicant: Chia Ying Lee

Designer： Chia Ying Lee

公开(公告)号：USD571651S1

公开(公告)日：2008-06-24

申请号：US29286159

申请日：2007-04-25

Applicant: Chia Ying Lee

Designer： Chia Ying Lee

公开(公告)号：USD569222S1

公开(公告)日：2008-05-20

申请号：US29286162

申请日：2007-04-25

Applicant: Chia Ying Lee

Designer： Chia Ying Lee

公开(公告)号：USD563707S1

公开(公告)日：2008-03-11

申请号：US29286161

申请日：2007-04-25

Applicant: Chia Ying Lee

Designer： Chia Ying Lee