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    Dual SOI structure
    1.
    发明申请
    Dual SOI structure 有权
    双重SOI结构

    公开(公告)号：US20070102769A1

    公开(公告)日：2007-05-10

    申请号：US11268914

    申请日：2005-11-08

    申请人： Chiang-Ming Chuang ,  Kuang-Hsin Chen ,  I-Lu Wu

    发明人： Chiang-Ming Chuang ,  Kuang-Hsin Chen ,  I-Lu Wu

    IPC分类号： H01L29/76

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207 ,  H01L29/045

    摘要： A semiconductor structure having a hybrid crystal orientation is provided. The semiconductor structure includes an insulator layer, e.g., a buried oxide (BOX), on a first semiconductor layer, and a second semiconductor layer on the buried oxide, wherein the first and second semiconductor layers have a first and a second crystal orientation, respectively. A first region of the second semiconductor layer is replaced with an epitaxially grown layer of the first semiconductor layer, thereby providing a substrate having a first region with a first crystal orientation and a second region with a second crystal orientation. An isolation structure is formed to isolate the first and second regions. Thereafter, NMOS and PMOS transistors may be formed on the substrate in the region having the crystal orientation that is the most appropriate.

    摘要翻译： 提供具有混合晶体取向的半导体结构。 所述半导体结构包括在第一半导体层上的绝缘体层，例如掩埋氧化物（BOX）和所述掩埋氧化物上的第二半导体层，其中所述第一和第二半导体层分别具有第一和第二晶体取向 。 用第一半导体层的外延生长层代替第二半导体层的第一区域，从而提供具有第一晶体取向的第一区域和具有第二晶体取向的第二区域的衬底。 形成隔离结构以隔离第一和第二区域。 此后，可以在具有最合适的晶体取向的区域中的衬底上形成NMOS和PMOS晶体管。

    Dual SOI structure
    2.
    发明授权
    Dual SOI structure 有权
    双重SOI结构

    公开(公告)号：US07986029B2

    公开(公告)日：2011-07-26

    申请号：US11268914

    申请日：2005-11-08

    申请人： Chiang-Ming Chuang ,  Kuang-Hsin Chen ,  I-Lu Wu

    发明人： Chiang-Ming Chuang ,  Kuang-Hsin Chen ,  I-Lu Wu

    IPC分类号： H01L29/06

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207 ,  H01L29/045

    摘要： A semiconductor structure having a hybrid crystal orientation is provided. The semiconductor structure includes an insulator layer, e.g., a buried oxide (BOX), on a first semiconductor layer, and a second semiconductor layer on the buried oxide, wherein the first and second semiconductor layers have a first and a second crystal orientation, respectively. A first region of the second semiconductor layer is replaced with an epitaxially grown layer of the first semiconductor layer, thereby providing a substrate having a first region with a first crystal orientation and a second region with a second crystal orientation. An isolation structure is formed to isolate the first and second regions. Thereafter, NMOS and PMOS transistors may be formed on the substrate in the region having the crystal orientation that is the most appropriate.

    摘要翻译： 提供具有混合晶体取向的半导体结构。 所述半导体结构包括在第一半导体层上的绝缘体层，例如掩埋氧化物（BOX）和所述掩埋氧化物上的第二半导体层，其中所述第一和第二半导体层分别具有第一和第二晶体取向 。 用第一半导体层的外延生长层代替第二半导体层的第一区域，从而提供具有第一晶体取向的第一区域和具有第二晶体取向的第二区域的衬底。 形成隔离结构以隔离第一和第二区域。 此后，可以在具有最合适的晶体取向的区域中的衬底上形成NMOS和PMOS晶体管。

    Composite gate structure in an integrated circuit
    3.
    发明授权
    Composite gate structure in an integrated circuit 有权
    集成电路中的复合栅极结构

    公开(公告)号：US07183596B2

    公开(公告)日：2007-02-27

    申请号：US11158764

    申请日：2005-06-22

    申请人： I-Lu Wu ,  Kuang-Hsin Chen ,  Liang-Kai Han

    发明人： I-Lu Wu ,  Kuang-Hsin Chen ,  Liang-Kai Han

    IPC分类号： H01L29/76

    CPC分类号： H01L21/823842 ,  H01L21/823857 ,  H01L29/785

    摘要： An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.

    摘要翻译： 提供一种具有复合栅结构的集成电路及其形成方法。 集成电路包括第一MOS器件，第二MOS器件和第三MOS器件。 第一MOS器件的栅极堆叠包括高k栅极电介质和高k栅极电介质上的第一金属栅极。 第二MOS器件的栅极堆叠包括在高k栅极电介质上的第二金属栅极。 第一金属门和第二金属门具有不同的功能。 第三MOS器件的栅极堆叠包括栅极电介质上的硅栅极。 硅栅极优选形成在第一MOS器件和第二MOS器件的栅极堆叠之上。

    Composite gate structure in an integrated circuit
    4.
    发明授权
    Composite gate structure in an integrated circuit 有权

    公开(公告)号：US07297587B2

    公开(公告)日：2007-11-20

    申请号：US11648964

    申请日：2007-01-03

    申请人： I-Lu Wu ,  Kuang-Hsin Chen ,  Liang-Kai Han

    发明人： I-Lu Wu ,  Kuang-Hsin Chen ,  Liang-Kai Han

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L21/823857 ,  H01L29/785

    摘要： An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.

    Composite gate structure in an integrated circuit
    5.
    发明申请
    Composite gate structure in an integrated circuit 有权

    公开(公告)号：US20070111425A1

    公开(公告)日：2007-05-17

    申请号：US11648964

    申请日：2007-01-03

    申请人： I-Lu Wu ,  Kuang-Hsin Chen ,  Liang-Kai Han

    发明人： I-Lu Wu ,  Kuang-Hsin Chen ,  Liang-Kai Han

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L21/823857 ,  H01L29/785

    摘要： An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.

    COMPOSITE GATE STRUCTURE IN AN INTEGRATED CIRCUIT
    6.
    发明申请
    COMPOSITE GATE STRUCTURE IN AN INTEGRATED CIRCUIT 有权
    集成电路中的复合门结构

    公开(公告)号：US20060289920A1

    公开(公告)日：2006-12-28

    申请号：US11158764

    申请日：2005-06-22

    申请人： I-Lu Wu ,  Kuang-Hsin Chen ,  Liang-Kai Han

    发明人： I-Lu Wu ,  Kuang-Hsin Chen ,  Liang-Kai Han

    IPC分类号： H01L29/76 ,  H01L29/94

    CPC分类号： H01L21/823842 ,  H01L21/823857 ,  H01L29/785

    摘要： An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.

    摘要翻译： 提供一种具有复合栅结构的集成电路及其形成方法。 集成电路包括第一MOS器件，第二MOS器件和第三MOS器件。 第一MOS器件的栅极堆叠包括高k栅极电介质和高k栅极电介质上的第一金属栅极。 第二MOS器件的栅极堆叠包括在高k栅极电介质上的第二金属栅极。 第一金属门和第二金属门具有不同的功能。 第三MOS器件的栅极堆叠包括栅极电介质上的硅栅极。 硅栅极优选形成在第一MOS器件和第二MOS器件的栅极堆叠之上。

    CMOS on SOI substrates with hybrid crystal orientations
    7.
    发明申请
    CMOS on SOI substrates with hybrid crystal orientations 有权
    CMOS在具有杂化晶体取向的SOI衬底上

    公开(公告)号：US20060292770A1

    公开(公告)日：2006-12-28

    申请号：US11290914

    申请日：2005-11-30

    申请人： I-Lu Wu ,  Chung-Te Lin ,  Tan-Chen Lee

    发明人： I-Lu Wu ,  Chung-Te Lin ,  Tan-Chen Lee

    IPC分类号： H01L21/337 ,  H01L21/8238

    CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/785

    摘要： Methods and structures for CMOS devices with hybrid crystal orientations using double SOI substrates is provided. In accordance with preferred embodiments, a manufacturing sequence includes the steps of forming an SOI silicon epitaxy layer after the step of forming shallow trench isolation regions. The preferred sequence allows hybrid SOI CMOS fabrication without encountering problems caused by forming STI regions after epitaxy. A preferred device includes an NFET on a {100} crystal orientation and a PFET on a {110} crystal orientation. An NMOS channel may be oriented along the direction, which is the direction of maximum electron mobility for a {100} substrate. A PMOS channel may be oriented along the direction, which is the direction where hole mobility is maximum for a {110} substrate.

    摘要翻译： 提供了使用双重SOI衬底的具有混合晶体取向的CMOS器件的方法和结构。 根据优选实施例，制造顺序包括在形成浅沟槽隔离区的步骤之后形成SOI硅外延层的步骤。 优选的顺序允许混合SOI CMOS制造，而不会遇到在外延后形成STI区域引起的问题。 优选的器件包括{100}晶体取向的NFET和{110}晶体取向的PFET。 可以沿着<100>方向取向NMOS沟道，这是{100}衬底的最大电子迁移率的方向。 可以沿着<110>方向取向PMOS沟道，这是{110}衬底的空穴迁移率最大的方向。

    Capacitors Integrated with Metal Gate Formation
    8.
    发明申请
    Capacitors Integrated with Metal Gate Formation 有权
    电容器与金属门形成集成

    公开(公告)号：US20090090951A1

    公开(公告)日：2009-04-09

    申请号：US11868856

    申请日：2007-10-08

    申请人： Chung-Long Chang ,  David Ding-Chung Lu ,  Chia-Yi Chen ,  I-Lu Wu

    发明人： Chung-Long Chang ,  David Ding-Chung Lu ,  Chia-Yi Chen ,  I-Lu Wu

    IPC分类号： H01L27/108

    CPC分类号： H01L27/11568 ,  H01L23/5223 ,  H01L27/0629 ,  H01L27/105 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure including a capacitor having increased capacitance and improved electrical performance is provided. The semiconductor structure includes a substrate; and a capacitor over the substrate. The capacitor includes a first layer including a first capacitor electrode and a second capacitor electrode, wherein the first capacitor electrode is formed of a metal-containing material and is free from polysilicon. The semiconductor structure further includes a MOS device including a gate dielectric over the substrate; and a metal-containing gate electrode on the gate dielectric, wherein the metal-containing gate electrode is formed of a same material, and has a same thickness, as the first capacitor electrode.

    摘要翻译： 提供了包括具有增加的电容和改善的电性能的电容器的半导体结构。 半导体结构包括基板; 以及在基板上的电容器。 电容器包括：第一层，包括第一电容器电极和第二电容器电极，其中第一电容器电极由含金属的材料形成并且不含多晶硅。 所述半导体结构还包括：在所述基板上包括栅电介质的MOS器件; 以及栅极电介质上的含金属的栅电极，其中所述含金属的栅电极由与所述第一电容器电极相同的材料形成，并且具有相同的厚度。

    Capacitors integrated with metal gate formation
    9.
    发明授权
    Capacitors integrated with metal gate formation 有权
    电容器与金属栅极结合

    公开(公告)号：US08022458B2

    公开(公告)日：2011-09-20

    申请号：US11868856

    申请日：2007-10-08

    申请人： Chung-Long Chang ,  David Ding-Chung Lu ,  Chia-Yi Chen ,  I-Lu Wu

    发明人： Chung-Long Chang ,  David Ding-Chung Lu ,  Chia-Yi Chen ,  I-Lu Wu

    IPC分类号： H01L27/108

    CPC分类号： H01L27/11568 ,  H01L23/5223 ,  H01L27/0629 ,  H01L27/105 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure including a capacitor having increased capacitance and improved electrical performance is provided. The semiconductor structure includes a substrate; and a capacitor over the substrate. The capacitor includes a first layer including a first capacitor electrode and a second capacitor electrode, wherein the first capacitor electrode is formed of a metal-containing material and is free from polysilicon. The semiconductor structure further includes a MOS device including a gate dielectric over the substrate; and a metal-containing gate electrode on the gate dielectric, wherein the metal-containing gate electrode is formed of a same material, and has a same thickness, as the first capacitor electrode.

    摘要翻译： 提供了包括具有增加的电容和改善的电性能的电容器的半导体结构。 半导体结构包括基板; 以及在基板上的电容器。 电容器包括：第一层，包括第一电容器电极和第二电容器电极，其中第一电容器电极由含金属的材料形成并且不含多晶硅。 所述半导体结构还包括：在所述基板上包括栅电介质的MOS器件; 以及栅极电介质上的含金属的栅电极，其中所述含金属的栅电极由与所述第一电容器电极相同的材料形成，并且具有相同的厚度。

    CMOS on SOI substrates with hybrid crystal orientations
    10.
    发明授权
    CMOS on SOI substrates with hybrid crystal orientations 有权
    CMOS在具有杂化晶体取向的SOI衬底上

    公开(公告)号：US07432149B2

    公开(公告)日：2008-10-07

    申请号：US11290914

    申请日：2005-11-30

    申请人： I-Lu Wu ,  Chung-Te Lin ,  Tan-Chen Lee

    发明人： I-Lu Wu ,  Chung-Te Lin ,  Tan-Chen Lee

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/785

    摘要： Methods and structures for CMOS devices with hybrid crystal orientations using double SOI substrates is provided. In accordance with preferred embodiments, a manufacturing sequence includes the steps of forming an SOI silicon epitaxy layer after the step of forming shallow trench isolation regions. The preferred sequence allows hybrid SOI CMOS fabrication without encountering problems caused by forming STI regions after epitaxy. A preferred device includes an NFET on a {100} crystal orientation and a PFET on a {110} crystal orientation. An NMOS channel may be oriented along the direction, which is the direction of maximum electron mobility for a {100} substrate. A PMOS channel may be oriented along the direction, which is the direction where hole mobility is maximum for a {110} substrate.

    摘要翻译： 提供了使用双重SOI衬底的具有混合晶体取向的CMOS器件的方法和结构。 根据优选实施例，制造顺序包括在形成浅沟槽隔离区的步骤之后形成SOI硅外延层的步骤。 优选的顺序允许混合SOI CMOS制造，而不会遇到在外延后形成STI区域引起的问题。 优选的器件包括{100}晶体取向的NFET和{110}晶体取向的PFET。 可以沿着<100>方向取向NMOS沟道，这是{100}衬底的最大电子迁移率的方向。 可以沿着<110>方向取向PMOS沟道，这是{110}衬底的空穴迁移率最大的方向。