公开(公告)号：US20080157266A1

公开(公告)日：2008-07-03

申请号：US12049452

申请日：2008-03-17

申请人： Chien-Hao Chen ,  Vincent S. Chang ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Chien-Hao Chen ,  Vincent S. Chang ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L21/762

CPC分类号： H01L21/76235

摘要： A new and improved liner modification method for a liner oxide layer in an STI trench is disclosed. According to the method, an STI trench is etched in a substrate and a liner oxide layer is formed on the trench surfaces by oxidation techniques. The method further includes pre-treatment of the trench surfaces using a nitrogen-containing gas prior to formation of the liner oxide layer, post-formation nitridation of the liner oxide layer, or both pre-treatment of the trench surfaces and post-formation nitridation of the liner oxide layer. The liner modification method of the present invention optimizes the inverse narrow width effect (INWE) and gate oxide integrity (GOI) of STI structures and prevents diffusion of dopant into the liner oxide layer during subsequent processing.

摘要翻译： 公开了一种用于STI沟槽中的衬垫氧化物层的新的改进的衬垫修改方法。 根据该方法，在衬底中蚀刻STI沟槽，并且通过氧化技术在沟槽表面上形成衬垫氧化物层。 该方法还包括在形成衬垫氧化物层之前使用含氮气体预处理沟槽表面，衬里氧化物层的形成后氮化或沟槽表面的预处理和后形成氮化 的衬里氧化物层。 本发明的衬垫修改方法优化STI结构的反窄窄度效应（INWE）和栅极氧化物完整性（GOI），并防止掺杂剂在随后的处理期间扩散到衬里氧化物层中。

公开(公告)号：US07361572B2

公开(公告)日：2008-04-22

申请号：US11059728

申请日：2005-02-17

申请人： Chien-Hao Chen ,  Vincent S. Chang ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Chien-Hao Chen ,  Vincent S. Chang ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L21/76

CPC分类号： H01L21/76235

摘要： A new and improved liner modification method for a liner oxide layer in an STI trench is disclosed. According to the method, an STI trench is etched in a substrate and a liner oxide layer is formed on the trench surfaces by oxidation techniques. The method further includes pre-treatment of the trench surfaces using a nitrogen-containing gas prior to formation of the liner oxide layer, post-formation nitridation of the liner oxide layer, or both pre-treatment of the trench surfaces and post-formation nitridation of the liner oxide layer. The liner modification method of the present invention optimizes the inverse narrow width effect (INWE) and gate oxide integrity (GOI) of STI structures and prevents diffusion of dopant into the liner oxide layer during subsequent processing.

摘要翻译： 公开了一种用于STI沟槽中的衬垫氧化物层的新的改进的衬垫修改方法。 根据该方法，在衬底中蚀刻STI沟槽，并且通过氧化技术在沟槽表面上形成衬垫氧化物层。 该方法还包括在形成衬垫氧化物层之前使用含氮气体预处理沟槽表面，衬里氧化物层的形成后氮化或沟槽表面的预处理和后形成氮化 的衬里氧化物层。 本发明的衬垫修改方法优化STI结构的反窄窄度效应（INWE）和栅极氧化物完整性（GOI），并防止掺杂剂在随后的处理期间扩散到衬里氧化物层中。

公开(公告)号：US07166525B2

公开(公告)日：2007-01-23

申请号：US10758317

申请日：2004-01-15

申请人： Vincent S. Chang ,  Chia-Lin Chen ,  Chi-Chun Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Chien-Hao Chen

发明人： Vincent S. Chang ,  Chia-Lin Chen ,  Chi-Chun Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Chien-Hao Chen

IPC分类号： H01L21/4763 ,  H01L21/3205

CPC分类号： H01L29/518 ,  H01L21/28123 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3105 ,  H01L21/3144 ,  H01L21/32137 ,  H01L29/6659

摘要： A method of defining a conductive gate structure for a MOSFET device wherein the etch rate selectivity of the conductive gate material to an underlying insulator layer is optimized, has been developed. After formation of a nitrided silicon dioxide layer, to be used as for the MOSFET gate insulator layer, a high temperature hydrogen anneal procedure is performed. The high temperature anneal procedure replaces nitrogen components in a top portion of the nitrided silicon dioxide gate insulator layer with hydrogen components. The etch rate of the hydrogen annealed layer in specific dry etch ambients is now decreased when compared to the non-hydrogen annealed nitrided silicon dioxide counterpart. Thus the etch rate selectivity of conductive gate material to underlying gate insulator material is increased when employing the slower etching hydrogen annealed nitrided silicon dioxide layer.

摘要翻译： 已经开发了限定用于MOSFET器件的导电栅极结构的方法，其中导电栅极材料对下面的绝缘体层的蚀刻速率选择性被优化。 在形成用于MOSFET栅极绝缘体层的氮化二氧化硅层之后，进行高温氢退火处理。 高温退火程序用氢组分替代氮化二氧化硅栅极绝缘体层的顶部中的氮组分。 当与非氢退火氮化二氧化硅对应物相比时，特定干蚀刻环境中的氢退火层的蚀刻速率现在降低。 因此，当采用较慢的蚀刻氢退火氮化二氧化硅层时，导电栅极材料对底层栅极绝缘体材料的蚀刻速率选择性增加。

公开(公告)号：US07176138B2

公开(公告)日：2007-02-13

申请号：US10970090

申请日：2004-10-21

申请人： Chien-Hao Chen ,  Vincent S. Chang ,  Ji-Yi Yang ,  Chia-Lin Chen ,  Tze-Liang Lee

发明人： Chien-Hao Chen ,  Vincent S. Chang ,  Ji-Yi Yang ,  Chia-Lin Chen ,  Tze-Liang Lee

IPC分类号： H01L21/311

CPC分类号： H01L21/76232

摘要： A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectively forming a first insulating layer lining the STI trench over said exposed substrate portions only; backfilling the STI trench with a second insulating layer; planarizing the second insulating layer; and, carrying out a wet etching process to remove the uppermost hardmask layer.

摘要翻译： 一种用于形成无自由度的氮化物衬底浅沟槽隔离（STI）特征的方法，包括提供包括延伸穿过最上面的硬掩模层的STI沟槽的衬底，暴露衬底部分的衬底的厚度; 仅在所述暴露的衬底部分上选择性地形成衬在STI沟槽上的第一绝缘层; 用第二绝缘层回填STI沟槽; 平面化第二绝缘层; 并进行湿蚀刻处理以去除最上面的硬掩模层。

公开(公告)号：US07327009B2

公开(公告)日：2008-02-05

申请号：US11620085

申请日：2007-01-05

申请人： Chien-Hao Chen ,  Vincent S. Chang ,  Ji-Yi Yang ,  Chia-Lin Chen ,  Tze-Liang Lee

发明人： Chien-Hao Chen ,  Vincent S. Chang ,  Ji-Yi Yang ,  Chia-Lin Chen ,  Tze-Liang Lee

IPC分类号： H01L29/00

CPC分类号： H01L21/76232

摘要： A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectively forming a first insulating layer lining the STI trench over said exposed substrate portions only; backfilling the STI trench with a second insulating layer; planarizing the second insulating layer; and, carrying out a wet etching process to remove the uppermost hardmask layer.

摘要翻译： 一种用于形成无自由度的氮化物衬底浅沟槽隔离（STI）特征的方法，包括提供包括延伸穿过最上面的硬掩模层的STI沟槽的衬底，暴露衬底部分的衬底的厚度; 仅在所述暴露的衬底部分上选择性地形成衬在STI沟槽上的第一绝缘层; 用第二绝缘层回填STI沟槽; 平面化第二绝缘层; 并进行湿蚀刻处理以去除最上面的硬掩模层。

公开(公告)号：US06864109B2

公开(公告)日：2005-03-08

申请号：US10625410

申请日：2003-07-23

申请人： Vincent S. Chang ,  Chi-Chun Chen ,  Chun-Lin Wu ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Vincent S. Chang ,  Chi-Chun Chen ,  Chun-Lin Wu ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： G01N21/71 ,  H01L21/314 ,  H01L29/78 ,  H01L21/26 ,  H01L21/66

CPC分类号： H01J37/32935 ,  G01N21/71 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/7833

摘要： A method of determining a composition of an integrated circuit feature, including collecting intensity data representative of spectral wavelengths of radiant energy generated by a plasma during plasma nitridation of an integrated circuit feature disposed on a substrate, analysing the in intensity data to determine a peak intensity at one of the wavelengths, and determining a component concentration of the feature based on the peak intensity.

摘要翻译： 一种确定集成电路特征的组成的方法，包括收集表示在等离子体中等离子体产生的辐射能的光谱波长的强度数据，所述等离子体在等离子体氮化期间设置在基板上的集成电路特征，分析强度数据以确定峰强度 在一个波长处，并且基于峰值强度确定特征的分量浓度。

公开(公告)号：US07824990B2

公开(公告)日：2010-11-02

申请号：US11328933

申请日：2006-01-10

申请人： Vincent S. Chang ,  Fong-Yu Yen ,  Peng-Soon Lim ,  Jin Ying ,  Hun-Jan Tao

发明人： Vincent S. Chang ,  Fong-Yu Yen ,  Peng-Soon Lim ,  Jin Ying ,  Hun-Jan Tao

IPC分类号： H01L21/336 ,  H01L21/31

CPC分类号： H01L21/02175 ,  H01L21/0228 ,  H01L21/02337 ,  H01L21/28079 ,  H01L21/28194 ,  H01L21/3141 ,  H01L21/31645 ,  H01L29/1054 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor structure having a high-k dielectric and its method of manufacture is provided. A method includes forming a first dielectric layer over the substrate, a metal layer over the first dielectric layer, and a second dielectric layer over the metal layer. A method further includes annealing the substrate in an oxidizing ambient until the three layers form a homogenous high-k dielectric layer. Forming the first and second dielectric layers comprises a non-plasma deposition process such atomic layer deposition (ALD), or chemical vapor deposition (CVD). A semiconductor device having a high-k dielectric comprises an amorphous high-k dielectric layer, wherein the amorphous high-k dielectric layer comprises a first oxidized metal and a second oxidized metal. The atomic ratios of all oxidized metals are substantially uniformly within the amorphous high-k dielectric layer.

摘要翻译： 提供具有高k电介质的半导体结构及其制造方法。 一种方法包括在衬底上形成第一介电层，在第一介电层上形成金属层，在金属层上方形成第二电介质层。 一种方法还包括在氧化环境中退火衬底，直到三层形成均匀的高k电介质层。 形成第一和第二电介质层包括诸如原子层沉积（ALD）或化学气相沉积（CVD）的非等离子体沉积工艺。 具有高k电介质的半导体器件包括非晶高k电介质层，其中非晶高k电介质层包括第一氧化金属和第二氧化金属。 所有氧化金属的原子比在非晶高k电介质层内基本均匀。

公开(公告)号：US20080001237A1

公开(公告)日：2008-01-03

申请号：US11478476

申请日：2006-06-29

申请人： Vincent S. Chang ,  Peng-Fu Hsu ,  Fong-Yu Yen ,  Yong-Tian Hou ,  Jin Ying ,  Hun-Jan Tao

发明人： Vincent S. Chang ,  Peng-Fu Hsu ,  Fong-Yu Yen ,  Yong-Tian Hou ,  Jin Ying ,  Hun-Jan Tao

IPC分类号： H01L29/78

CPC分类号： H01L29/513 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823871 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/7833

摘要： Disclosed is a semiconductor device having a substrate, an interfacial layer formed on said substrate, a nitrogen-containing high dielectric constant (high-k) layer formed on said interfacial layer, and a metal electrode on said nitrogen-containing high-k layer. Also disclosed is a method of forming a transistor including forming on a substrate an interfacial layer comprising silicon and oxygen, depositing on the interfacial layer a high-k dielectric material, nitriding the high-k dielectric material, depositing a metal layer on the high-k dielectric material, and patterning the metal layer, the high-k dielectric material, and the interfacial layer to form a gate stack.

摘要翻译： 公开了一种半导体器件，其具有基板，在所述基板上形成的界面层，在所述界面层上形成的含氮高介电常数（高k）层和所述含氮高k层上的金属电极。 还公开了一种形成晶体管的方法，包括在衬底上形成包含硅和氧的界面层，在界面层上沉积高k电介质材料，氮化高k电介质材料，在高介电材料上沉积金属层， k电介质材料，并且图案化金属层，高k电介质材料和界面层以形成栅极堆叠。