公开(公告)号：US07981727B2

公开(公告)日：2011-07-19

申请号：US11987232

申请日：2007-11-28

申请人： Chien-Hung Liu ,  Sih-Dian Lee

发明人： Chien-Hung Liu ,  Sih-Dian Lee

IPC分类号： H01L21/00

CPC分类号： H01L31/0203 ,  H01L23/3114 ,  H01L24/05 ,  H01L24/13 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14687 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/00

摘要： Electronic device wafer level scale packages and fabrication methods thereof. A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A first trench is formed by etching the semiconductor exposing an inter-layered dielectric layer. An insulating layer is conformably deposited on the back of the semiconductor substrate. The insulating layer on the bottom of the first trench is removed to create a second trench. The insulating layer and the ILD layer are sequentially removed exposing part of a pair of contact pads. A conductive layer is conformably formed on the back of the semiconductor. After the conductive layer is patterned, the conductive layer and the contact pads construct an S-shaped connection. Next, an exterior connection and terminal contact pads are subsequently formed.

摘要翻译： 电子装置晶圆级规包装及其制造方法。 提供了形成有多个电子器件的半导体晶片。 半导体晶片与支撑基板结合。 半导体衬底的背面变薄。 通过蚀刻暴露层间电介质层的半导体形成第一沟槽。 绝缘层顺应地沉积在半导体衬底的背面上。 去除第一沟槽底部的绝缘层以产生第二沟槽。 依次去除绝缘层和ILD层，暴露一对接触焊盘的一部分。 导电层顺应地形成在半导体的背面上。 导电层被图案化之后，导电层和接触垫构成S形连接。 接下来，随后形成外部连接和端子接触焊盘。

公开(公告)号：US20110237018A1

公开(公告)日：2011-09-29

申请号：US13152891

申请日：2011-06-03

申请人： Chien-Hung LIU ,  Sih-Dian Lee

发明人： Chien-Hung LIU ,  Sih-Dian Lee

IPC分类号： H01L31/02 ,  H01L21/18 ,  H01L21/78

CPC分类号： H01L31/0203 ,  H01L23/3114 ,  H01L24/05 ,  H01L24/13 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14687 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/00

摘要： Electronic device wafer level scale packages and fabrication methods thereof A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A first trench is formed by etching the semiconductor exposing an inter-layered dielectric layer. An insulating layer is conformably deposited on the back of the semiconductor substrate. The insulating layer on the bottom of the first trench is removed to create a second trench. The insulating layer and the ILD layer are sequentially removed exposing part of a pair of contact pads. A conductive layer is conformably formed on the back of the semiconductor. After the conductive layer is patterned, the conductive layer and the contact pads construct an S-shaped connection. Next, an exterior connection and terminal contact pads are subsequently formed.

摘要翻译： 电子器件晶片级规包装及其制造方法提供了一种其上形成有多个电子器件的半导体晶片。 半导体晶片与支撑基板结合。 半导体衬底的背面变薄。 通过蚀刻暴露层间电介质层的半导体形成第一沟槽。 绝缘层顺应地沉积在半导体衬底的背面上。 去除第一沟槽底部的绝缘层以产生第二沟槽。 依次去除绝缘层和ILD层，暴露一对接触焊盘的一部分。 导电层顺应地形成在半导体的背面上。 导电层被图案化之后，导电层和接触垫构成S形连接。 接下来，随后形成外部连接和端子接触焊盘。

公开(公告)号：US20090050996A1

公开(公告)日：2009-02-26

申请号：US11987232

申请日：2007-11-28

申请人： Chien-Hung Liu ,  Sih-Dian Lee

发明人： Chien-Hung Liu ,  Sih-Dian Lee

IPC分类号： H01L31/0203 ,  H01L31/18 ,  H01L21/58 ,  H01L23/15

CPC分类号： H01L31/0203 ,  H01L23/3114 ,  H01L24/05 ,  H01L24/13 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14687 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/00

摘要： Electronic device wafer level scale packages and fabrication methods thereof. A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A first trench is formed by etching the semiconductor exposing an inter-layered dielectric layer. An insulating layer is conformably deposited on the back of the semiconductor substrate. The insulating layer on the bottom of the first trench is removed to create a second trench. The insulating layer and the ILD layer are sequentially removed exposing part of a pair of contact pads. A conductive layer is conformably formed on the back of the semiconductor. After the conductive layer is patterned, the conductive layer and the contact pads construct an S-shaped connection. Next, an exterior connection and terminal contact pads are subsequently formed.

摘要翻译： 电子装置晶圆级规包装及其制造方法。 提供了形成有多个电子器件的半导体晶片。 半导体晶片与支撑基板结合。 半导体衬底的背面变薄。 通过蚀刻暴露层间电介质层的半导体形成第一沟槽。 绝缘层顺应地沉积在半导体衬底的背面上。 去除第一沟槽底部的绝缘层以产生第二沟槽。 依次去除绝缘层和ILD层，暴露一对接触焊盘的一部分。 导电层顺应地形成在半导体的背面上。 导电层被图案化之后，导电层和接触垫构成S形连接。 接下来，随后形成外部连接和端子接触焊盘。

公开(公告)号：US08309398B2

公开(公告)日：2012-11-13

申请号：US13152891

申请日：2011-06-03

申请人： Chien-Hung Liu ,  Sih-Dian Lee

发明人： Chien-Hung Liu ,  Sih-Dian Lee

IPC分类号： H01L21/00 ,  H01L21/78

CPC分类号： H01L31/0203 ,  H01L23/3114 ,  H01L24/05 ,  H01L24/13 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14687 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/00

摘要： Electronic device wafer level scale packages and fabrication methods thereof. A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A first trench is formed by etching the semiconductor exposing an inter-layered dielectric layer. An insulating layer is conformably deposited on the back of the semiconductor substrate. The insulating layer on the bottom of the first trench is removed to create a second trench. The insulating layer and the ILD layer are sequentially removed exposing part of a pair of contact pads. A conductive layer is conformably formed on the back of the semiconductor. After the conductive layer is patterned, the conductive layer and the contact pads construct an S-shaped connection. Next, an exterior connection and terminal contact pads are subsequently formed.

摘要翻译： 电子装置晶圆级规包装及其制造方法。 提供了形成有多个电子器件的半导体晶片。 半导体晶片与支撑基板结合。 半导体衬底的背面变薄。 通过蚀刻暴露层间电介质层的半导体形成第一沟槽。 绝缘层顺应地沉积在半导体衬底的背面上。 去除第一沟槽底部的绝缘层以产生第二沟槽。 依次去除绝缘层和ILD层，暴露一对接触焊盘的一部分。 导电层顺应地形成在半导体的背面上。 导电层被图案化之后，导电层和接触垫构成S形连接。 接下来，随后形成外部连接和端子接触焊盘。

公开(公告)号：US20090050995A1

公开(公告)日：2009-02-26

申请号：US11987227

申请日：2007-11-28

申请人： Chien-Hung Liu ,  Sih-Dian Lee

发明人： Chien-Hung Liu ,  Sih-Dian Lee

IPC分类号： H01L31/0203 ,  H01L23/15 ,  H01L31/18 ,  H01L21/58

CPC分类号： H01L31/0203 ,  H01L23/3114 ,  H01L24/13 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14687 ,  H01L29/0657 ,  H01L2224/05001 ,  H01L2224/05548 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/00

摘要： Electronic device wafer level scale packages and fabrication methods thereof. A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A trench is formed by etching the semiconductor exposing an inter-layered dielectric (ILD) layer. An insulating layer is conformably deposited on the back of the semiconductor substrate. The insulating layer on the bottom of the trench is removed, and the ILD layer is subsequently removed exposing part of a pair of contact pads. A conductive layer is conformably formed on the back of the semiconductor. After the conductive layer is patterned, the conductive layer and the contact pads construct an L-shaped connection. Next, an exterior connection and terminal contact pads are subsequently formed.

摘要翻译： 电子装置晶圆级规包装及其制造方法。 提供了形成有多个电子器件的半导体晶片。 半导体晶片与支撑基板结合。 半导体衬底的背面变薄。 通过蚀刻暴露层间电介质（ILD）层的半导体形成沟槽。 绝缘层顺应地沉积在半导体衬底的背面上。 去除沟槽底部的绝缘层，随后去除暴露部分一对接触垫的ILD层。 导电层顺应地形成在半导体的背面上。 在导电层被图案化之后，导电层和接触垫构成L形连接。 接下来，随后形成外部连接和端子接触焊盘。