公开(公告)号：US06876016B2

公开(公告)日：2005-04-05

申请号：US10292773

申请日：2002-11-12

申请人： Chien-Ling Chan

发明人： Chien-Ling Chan

IPC分类号： H01L27/146 ,  H01L27/148

CPC分类号： H01L27/14609 ,  H01L27/1463

摘要： A method is disclosed for forming an image sensor. In a semiconductor wafer containing a p-type region an n-type connection region is formed within the p-type region. An n-type photodiode region is formed in the p-type region connected to the connection region. A field oxide isolation region is formed, having a part that is over portions of the n-type connection region and the n-type photodiode region. This part of the field oxide region covers the area where these regions are connected and extends into these regions. The edges of this part of the field oxide region fall within these regions, while leaving a distance between these edges and pn junctions formed by the connection region and the p-type region and the n-type photodiode region and p-type region. A gate oxide is formed over regions not covered by field oxide. An extended gate structure is formed extending from above this part of the field oxide isolation region to a distance beyond the connection region so as to accommodate a channel of an n-channel MOSFET. The drain region of the n-channel MOSFET is formed, with the connection region acting as the source. A blanket transparent insulating layer is deposited.

摘要翻译： 公开了一种用于形成图像传感器的方法。 在包含p型区域的半导体晶片中，在p型区域内形成有n型连接区域。 在与连接区域连接的p型区域中形成n型光电二极管区域。 形成具有在n型连接区域和n型光电二极管区域的部分之上的部分的场氧化物隔离区域。 场氧化物区域的这一部分覆盖这些区域连接并延伸到这些区域中的区域。 场氧化物区域的这些部分的边缘落在这些区域内，同时留下这些边缘与由连接区域和p型区域以及n型光电二极管区域和p型区域形成的pn结之间的距离。 在不被场氧化物覆盖的区域上形成栅极氧化物。 扩展的栅极结构从场氧化物隔离区的该部分的上方延伸到超出连接区的距离，以便容纳n沟道MOSFET的沟道。 形成n沟道MOSFET的漏极区域，其中连接区域用作源极。 沉积一层覆盖的透明绝缘层。

公开(公告)号：US06495391B1

公开(公告)日：2002-12-17

申请号：US10068056

申请日：2002-02-05

申请人： Chien-Ling Chan

发明人： Chien-Ling Chan

IPC分类号： H01L2100

CPC分类号： H01L27/14609 ,  H01L27/1463

摘要： A method is disclosed for forming an image sensor. In a semiconductor wafer containing a p-type region an n-type connection region is formed within the p-type region. An n-type photodiode region is formed in the p-type region connected to the connection region. A field oxide isolation region is formed, having a part that is over portions of the n-type connection region and the n-type photodiode region,. This part of the field oxide region covers the area where these regions are connected and extends into these regions. The edges of this part of the field oxide region fall within these regions, while leaving a distance between these edges and pn junctions formed by the connection region and the p-type region and the n-type photodiode region and p-type region. A gate oxide is formed over regions not covered by field oxide. An extended gate structure is formed extending from above this part of the field oxide isolation region to a distance beyond the connection region so as to accommodate a channel of an n-channel MOSFET. The drain region of the n-channel MOSFET is formed, with the connection region acting as the source. A blanket transparent insulating layer is deposited.

摘要翻译： 公开了一种用于形成图像传感器的方法。 在包含p型区域的半导体晶片中，在p型区域内形成有n型连接区域。 在与连接区域连接的p型区域中形成n型光电二极管区域。 形成具有在n型连接区域和n型光电二极管区域的部分之上的部分的场氧化物隔离区域。 场氧化物区域的这一部分覆盖这些区域连接并延伸到这些区域中的区域。 场氧化物区域的这些部分的边缘落在这些区域内，同时留下这些边缘与由连接区域和p型区域以及n型光电二极管区域和p型区域形成的pn结之间的距离。 在不被场氧化物覆盖的区域上形成栅极氧化物。 扩展的栅极结构从场氧化物隔离区的该部分的上方延伸到超出连接区的距离，以便容纳n沟道MOSFET的沟道。 形成n沟道MOSFET的漏极区域，其中连接区域用作源极。 沉积一层覆盖的透明绝缘层。

公开(公告)号：US20120241870A1

公开(公告)日：2012-09-27

申请号：US13373225

申请日：2011-11-08

申请人： Chien-Ling Chan ,  Yuh-Chyuan Wang ,  Hung-Der Su

发明人： Chien-Ling Chan ,  Yuh-Chyuan Wang ,  Hung-Der Su

IPC分类号： H01L27/06 ,  H01L21/8249

CPC分类号： H01L29/7322 ,  H01L27/0623 ,  H01L27/1052 ,  H01L29/66272

摘要： The present invention discloses a bipolar junction transistor (BJT) with surface protection and a manufacturing method thereof. The BJT includes: a first conductive type base, a second conductive type emitter, and a second conductive type collector, which are formed in a substrate, wherein the base is formed between and separates the emitter and the collector, and the base includes a base contact region functioning as an electrical contact node of the base; and a gate structure which is formed on the substrate between the base contact region and the second conductive type emitter.

摘要翻译： 本发明公开了一种具有表面保护的双极结型晶体管（BJT）及其制造方法。 BJT包括：形成在基板中的第一导电型基极，第二导电型发射极和第二导电型集电极，其中基极形成在发射极和集电极之间并分离，并且基极包括基极 接触区域用作基座的电接触节点; 以及栅极结构，其形成在所述基极接触区域和所述第二导电型发射极之间。

公开(公告)号：US20080153239A1

公开(公告)日：2008-06-26

申请号：US11805979

申请日：2007-05-25

申请人： Hung-Der Su ,  Ching-Yao Yang ,  Chien-Ling Chan

发明人： Hung-Der Su ,  Ching-Yao Yang ,  Chien-Ling Chan

IPC分类号： H01L21/336 ,  G03F1/00

CPC分类号： H01L21/823475 ,  H01L21/26586 ,  H01L21/76895 ,  H01L21/823425

摘要： According to the present invention, a semiconductor process for butting contact comprises: providing a substrate on which are formed two adjacent transistor gates; implanting a full area between the two adjacent transistor gates by a tilt angle, to form a lightly doped region of a first conductivity type; forming a heavily doped region of the first conductivity type and a heavily doped region of a second conductivity type in the area between the two adjacent transistor gates, in which the heavily doped region of the second conductivity type overrides the lightly doped region of the first conductivity type, and divides the heavily doped region of the first conductivity type into two areas; depositing a dielectric layer; and forming a butting contact in the dielectric layer which concurrently contacts the two divided heavily doped regions of the first conductivity type.

摘要翻译： 根据本发明，用于对接接触的半导体工艺包括：提供在其上形成两个相邻晶体管栅极的衬底; 在两个相邻的晶体管栅极之间以倾斜角注入全部区域，以形成第一导电类型的轻掺杂区域; 在所述两个相邻晶体管栅极之间的区域中形成第一导电类型的重掺杂区域和第二导电类型的重掺杂区域，其中所述第二导电类型的重掺杂区域覆盖所述第一导电类型的轻掺杂区域 并且将第一导电类型的重掺杂区域划分为两个区域; 沉积介电层; 以及在同时接触第一导电类型的两个分开的重掺杂区域的电介质层中形成对接触点。

公开(公告)号：US20090042395A1

公开(公告)日：2009-02-12

申请号：US12285709

申请日：2008-10-14

申请人： Chien-Ling Chan ,  Jing-Meng Liu ,  Hung-Der Su

发明人： Chien-Ling Chan ,  Jing-Meng Liu ,  Hung-Der Su

IPC分类号： H01L21/311

CPC分类号： H01L21/8249 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/823864

摘要： A two-step spacer etch is used for the formation of a spacer in CMOS fabrication. A dry etch is first applied to remove part of the spacer material on the silicon substrate and leave a thin layer of the spacer material remained on the silicon substrate. Then, a wet etch is applied to completely remove the thin layer of the spacer material on the silicon substrate. The wet etch has good etch selectivity between the spacer material and silicon, and thus will not damage the surface of the silicon substrate when the spacer is formed. Therefore, the BJT on the silicon substrate is prevented from junction leakage.

摘要翻译： 在CMOS制造中使用两步间隔物蚀刻来形成间隔物。 首先施加干蚀刻以去除硅衬底上的部分间隔物材料，并留下留在硅衬底上的间隔物材料的薄层。 然后，施加湿蚀刻以完全去除硅衬底上的间隔物材料的薄层。 湿蚀刻在间隔材料和硅之间具有良好的蚀刻选择性，因此当形成间隔物时不会损坏硅衬底的表面。 因此，防止硅衬底上的BJT结漏。