公开(公告)号：US07732289B2

公开(公告)日：2010-06-08

申请号：US11174683

申请日：2005-07-05

申请人： Chii-Ming Wu ,  Chih-Wei Chang ,  Pang-Yen Tsai ,  Chih-Chien Chang

发明人： Chii-Ming Wu ,  Chih-Wei Chang ,  Pang-Yen Tsai ,  Chih-Chien Chang

IPC分类号： H01L21/366

CPC分类号： H01L29/665 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7843

摘要： A method of forming MOS devices is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode over the gate dielectric, forming a source/drain region in the semiconductor substrate, forming an additional layer, preferably by epitaxial growth, on the source/drain region, and siliciding at least a top portion of the additional layer. The additional layer compensates for at least a portion of the semiconductor material lost during manufacturing processes and increases the distance between the source/drain silicide and the substrate. As a result, the leakage current is reduced. A transistor formed using the preferred embodiment preferably includes a silicide over the gate electrode wherein the silicide extends beyond a sidewall boundary of the gate electrode.

摘要翻译： 提供了一种形成MOS器件的方法。 该方法包括提供半导体衬底，在半导体衬底上形成栅极电介质，在栅极电介质上形成栅电极，在半导体衬底中形成源/漏区，在源上形成附加层，优选通过外延生长 /漏极区域，并且至少将附加层的顶部部分硅化。 附加层补偿在制造过程中损失的半导体材料的至少一部分，并且增加源极/漏极硅化物和衬底之间的距离。 结果，泄漏电流降低。 使用优选实施例形成的晶体管优选地包括在栅极上的硅化物，其中硅化物延伸超过栅电极的侧壁边界。

公开(公告)号：US20070010051A1

公开(公告)日：2007-01-11

申请号：US11174683

申请日：2005-07-05

申请人： Chii-Ming Wu ,  Chih-Wei Chang ,  Pang-Yen Tsai ,  Chih-Chien Chang

发明人： Chii-Ming Wu ,  Chih-Wei Chang ,  Pang-Yen Tsai ,  Chih-Chien Chang

IPC分类号： H01L21/8234 ,  H01L21/4763

CPC分类号： H01L29/665 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7843

摘要： A method of forming MOS devices is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode over the gate dielectric, forming a source/drain region in the semiconductor substrate, forming an additional layer, preferably by epitaxial growth, on the source/drain region, and siliciding at least a top portion of the additional layer. The additional layer compensates for at least a portion of the semiconductor material lost during manufacturing processes and increases the distance between the source/drain silicide and the substrate. As a result, the leakage current is reduced. A transistor formed using the preferred embodiment preferably includes a silicide over the gate electrode wherein the silicide extends beyond a sidewall boundary of the gate electrode.

摘要翻译： 提供了一种形成MOS器件的方法。 该方法包括提供半导体衬底，在半导体衬底上形成栅极电介质，在栅极电介质上形成栅电极，在半导体衬底中形成源/漏区，在源上形成附加层，优选通过外延生长 /漏极区域，并且至少将附加层的顶部部分硅化。 附加层补偿在制造过程中损失的半导体材料的至少一部分，并且增加源极/漏极硅化物和衬底之间的距离。 结果，泄漏电流降低。 使用优选实施例形成的晶体管优选地包括在栅极上的硅化物，其中硅化物延伸超过栅电极的侧壁边界。

公开(公告)号：US07129184B2

公开(公告)日：2006-10-31

申请号：US11001384

申请日：2004-12-01

申请人： Chih-Chien Chang ,  Shun Wu Lin ,  Pang-Yen Tsai ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Chih-Chien Chang ,  Shun Wu Lin ,  Pang-Yen Tsai ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L21/302

CPC分类号： H01L21/02658 ,  H01L21/02381 ,  H01L21/02532

摘要： A method of preparing a silicon layer or substrate surface for growing an epitaxial layer of SiGe thereon. The process comprises removing native oxide from the surface of the silicon with an HF solution, and then oxidizing the exposed silicon surface to form a chemically formed layer of silicon oxide of the process damaged silicon surface. The chemically formed layer of silicon oxide is then removed by a second HF cleaning process so as to leave a smooth silicon surface suitable for growing a SiGe layer.

摘要翻译： 一种制备用于在其上生长SiGe的外延层的硅层或衬底表面的方法。 该方法包括用HF溶液从硅表面除去天然氧化物，然后氧化暴露的硅表面以形成工艺损坏的硅表面的化学形成的氧化硅层。 然后通过第二HF清洗工艺除去化学形成的氧化硅层，以便留下适于生长SiGe层的光滑硅表面。

公开(公告)号：US07816217B2

公开(公告)日：2010-10-19

申请号：US11313768

申请日：2005-12-22

申请人： Li-Te S. Lin ,  Pang-Yen Tsai ,  Chih-Chien Chang ,  Tze-Liang Lee

发明人： Li-Te S. Lin ,  Pang-Yen Tsai ,  Chih-Chien Chang ,  Tze-Liang Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/02639 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02661

摘要： A method for manufacturing a semiconductor device includes providing a substrate comprising silicon, cleaning the substrate, performing a first low pressure chemical vapor deposition (LPCVD) process using a first source gas to selectively deposit a seeding layer of silicon (Si) over the substrate, performing a second LPCVD process using a second source gas to selectively deposit a first layer of silicon germanium (SiGe) over the layer of Si, the second source gas including hydrochloride at a first flow rate, and performing a third LPCVD process using a third source gas including hydrochloride at a second flow rate. The first flow rate is substantially lower than the second flow rate.

摘要翻译： 一种制造半导体器件的方法包括提供包括硅的衬底，清洁衬底，使用第一源气体执行第一低压化学气相沉积（LPCVD）工艺，以在衬底上选择性地沉积硅（Si）晶种层， 使用第二源气体执行第二LPCVD处理，以选择性地在所述Si层上沉积第一层硅锗（SiGe），所述第二源气体以第一流速包括盐酸盐，并且使用第三源进行第三LPCVD处理 气体包括盐酸盐以第二流量。 第一流速基本上低于第二流量。

公开(公告)号：US20060228850A1

公开(公告)日：2006-10-12

申请号：US11100053

申请日：2005-04-06

申请人： Pang-Yen Tsai ,  Chih-Chien Chang ,  Indira Yang ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Pang-Yen Tsai ,  Chih-Chien Chang ,  Indira Yang ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L21/8238 ,  H01L21/76

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66628

摘要： A method of reducing the pattern-loading effect for selective epitaxial growth. The method includes the steps of: forming a mask layer over a substrate; forming an isolation region in the substrate isolating an active region and a dummy active region; removing at least a portion of the mask layer in the active region and thus forming a first opening, the substrate being exposed through the first opening; removing at least a portion of the mask layer in the dummy active region and thus forming a second opening, the substrate being exposed through the second opening; and performing selective epitaxial growth simultaneously on the substrate in the first opening and second openings. By introducing the second opening wherein epitaxial growth occurs, the pattern density is more uniform and thus the pattern-loading effect is reduced.

摘要翻译： 降低选择性外延生长的图案负载效应的方法。 该方法包括以下步骤：在衬底上形成掩模层; 在所述衬底中形成隔离有源区和虚拟有源区的隔离区; 去除所述有源区域中的所述掩模层的至少一部分，从而形成第一开口，所述基板通过所述第一开口露出; 去除所述虚拟有源区域中的所述掩模层的至少一部分，从而形成第二开口，所述基板通过所述第二开口露出; 以及在所述第一开口和所述第二开口中的所述衬底上同时执行选择性外延生长。 通过引入其中发生外延生长的第二开口，图案密度更均匀，因此图案加载效应降低。

公开(公告)号：US20060113282A1

公开(公告)日：2006-06-01

申请号：US11001384

申请日：2004-12-01

申请人： Chih-Chien Chang ,  Shun Lin ,  Pang-Yen Tsai ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Chih-Chien Chang ,  Shun Lin ,  Pang-Yen Tsai ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： B44C1/22 ,  B08B6/00 ,  B08B3/00 ,  C03C25/68

CPC分类号： H01L21/02658 ,  H01L21/02381 ,  H01L21/02532

摘要： A method of preparing a silicon layer or substrate surface for growing an epitaxial layer of SiGe thereon. The process comprises removing native oxide from the surface of the silicon with an HF solution, and then oxidizing the exposed silicon surface to form a chemically formed layer of silicon oxide of the process damaged silicon surface. The chemically formed layer of silicon oxide is then removed by a second HF cleaning process so as to leave a smooth silicon surface suitable for growing a SiGe layer.

公开(公告)号：US20070148919A1

公开(公告)日：2007-06-28

申请号：US11313768

申请日：2005-12-22

申请人： Li-Te Lin ,  Pang-Yen Tsai ,  Chih-Chien Chang ,  Tze-Liang Lee

发明人： Li-Te Lin ,  Pang-Yen Tsai ,  Chih-Chien Chang ,  Tze-Liang Lee

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/02639 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02661

摘要： A method for manufacturing a semiconductor device includes providing a substrate comprising silicon, cleaning the substrate, performing a first low pressure chemical vapor deposition (LPCVD) process using a first source gas to selectively deposit a seeding layer of silicon (Si) over the substrate, performing a second LPCVD process using a second source gas to selectively deposit a first layer of silicon germanium (SiGe) over the layer of Si, the second source gas including hydrochloride at a first flow rate, and performing a third LPCVD process using a third source gas including hydrochloride at a second flow rate. The first flow rate is substantially lower than the second flow rate.

摘要翻译： 一种制造半导体器件的方法包括提供包括硅的衬底，清洁衬底，使用第一源气体执行第一低压化学气相沉积（LPCVD）工艺，以在衬底上选择性地沉积硅（Si）晶种层， 使用第二源气体执行第二LPCVD处理，以选择性地在所述Si层上沉积第一层硅锗（SiGe），所述第二源气体以第一流速包括盐酸盐，并且使用第三源进行第三LPCVD处理 气体包括盐酸盐以第二流量。 第一流速基本上低于第二流量。

公开(公告)号：US08987813B2

公开(公告)日：2015-03-24

申请号：US13571366

申请日：2012-08-10

申请人： Chiu-Te Lee ,  Ke-Feng Lin ,  Chih-Chien Chang ,  Wei-Lin Chen ,  Chih-Chung Wang

发明人： Chiu-Te Lee ,  Ke-Feng Lin ,  Chih-Chien Chang ,  Wei-Lin Chen ,  Chih-Chung Wang

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08

CPC分类号： H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66704 ,  H01L29/7825

摘要： A high voltage metal-oxide-semiconductor transistor device includes a substrate, at least an isolation structure formed in the substrate, a gate formed on the substrate, and a source region and a drain region formed in the substrate at respective sides of the gate. The isolation structure further includes a recess. The gate includes a first gate portion formed on a surface of the substrate and a second gate portion downwardly extending from the first gate portion and formed in the recess.

摘要翻译： 高压金属氧化物半导体晶体管器件包括至少形成在衬底中的隔离结构的衬底，形成在衬底上的栅极，以及形成在栅极各侧的衬底中的源极区和漏极区。 隔离结构还包括凹部。 栅极包括形成在基板的表面上的第一栅极部分和从第一栅极部分向下延伸并形成在凹部中的第二栅极部分。

公开(公告)号：US20140042527A1

公开(公告)日：2014-02-13

申请号：US13571366

申请日：2012-08-10

申请人： Chiu-Te Lee ,  Ke-Feng Lin ,  Chih-Chien Chang ,  Wei-Lin Chen ,  Chih-Chung Wang

发明人： Chiu-Te Lee ,  Ke-Feng Lin ,  Chih-Chien Chang ,  Wei-Lin Chen ,  Chih-Chung Wang

IPC分类号： H01L29/78

CPC分类号： H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66704 ,  H01L29/7825

摘要： A high voltage metal-oxide-semiconductor transistor device includes a substrate, at least an isolation structure formed in the substrate, a gate formed on the substrate, and a source region and a drain region formed in the substrate at respective sides of the gate. The isolation structure further includes a recess. The gate includes a first gate portion formed on a surface of the substrate and a second gate portion downwardly extending from the first gate portion and formed in the recess.

摘要翻译： 高压金属氧化物半导体晶体管器件包括至少形成在衬底中的隔离结构的衬底，形成在衬底上的栅极，以及形成在栅极各侧的衬底中的源极区和漏极区。 隔离结构还包括凹部。 栅极包括形成在基板的表面上的第一栅极部分和从第一栅极部分向下延伸并形成在凹部中的第二栅极部分。

公开(公告)号：US20070057287A1

公开(公告)日：2007-03-15

申请号：US11227592

申请日：2005-09-15

申请人： Li-Te Lin ,  Chih-Chien Chang ,  Tze-Liang Lee

发明人： Li-Te Lin ,  Chih-Chien Chang ,  Tze-Liang Lee

IPC分类号： H01L31/00

CPC分类号： H01L29/1083 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： MOS devices having localized stressors are provided. Embodiments of the invention comprise a gate electrode formed over a substrate and source/drain regions formed on either side of the gate electrode. The source/drain regions include an embedded stressor and a capping layer on the embedded stressor. Preferably, the embedded stressor has a lattice spacing greater than the substrate lattice spacing. In a preferred embodiment, the substrate is silicon and the embedded stressor is silicon germanium. A method of manufacturing is also provided, wherein strained PMOS and NMOS transistors may be formed simultaneously.

摘要翻译： 提供具有局部应激源的MOS器件。 本发明的实施例包括形成在衬底上的栅电极和形成在栅电极的任一侧上的源/漏区。 源极/漏极区域包括嵌入的应力源和在嵌入的应力源上的覆盖层。 优选地，嵌入的应力器具有大于衬底晶格间距的晶格间距。 在优选实施例中，衬底是硅，并且嵌入的应力器是硅锗。 还提供了一种制造方法，其中应变PMOS和NMOS晶体管可以同时形成。