公开(公告)号：US07262456B2

公开(公告)日：2007-08-28

申请号：US11273668

申请日：2005-11-14

申请人： Ronald Kakoschke ,  Franz Schuler ,  Georg Tempel

发明人： Ronald Kakoschke ,  Franz Schuler ,  Georg Tempel

IPC分类号： H01L27/788 ,  H01L21/366

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11521

摘要： The disclosure relates to a bit line structure and an associated production method for the bit line structure. In the bit line structure, at least in a region of a second contact and a plurality of first contact adjoining the latter, an isolation trench is filled with an electrically conductive trench filling layer. The isolation trench connects to the first doping regions adjoining the second contact for the purpose of realizing a buried contact bypass line.

摘要翻译： 本公开涉及位线结构和相关联的位线结构的制造方法。 在位线结构中，至少在第二触点的区域和与其相邻的多个第一触点的区域中，隔离沟槽填充有导电沟槽填充层。 隔离沟槽连接到与第二接触相邻的第一掺杂区域，以实现埋地接触旁路线路。

公开(公告)号：US06881614B2

公开(公告)日：2005-04-19

申请号：US10600315

申请日：2003-06-20

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L21/336 ,  H01L21/8244 ,  H01L23/48 ,  H01L27/11 ,  H01L21/81 ,  H01L21/366

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： A new method and structure is created for a multi-transistor SRAM device. Standard processing steps are followed for the creation of CMOS devices of providing a patterned layer of gate material, of performing LDD impurity implants, of creating gate spacers. After the creation of the gate spacers, a new step of photoresist patterning and exposure is added. The mask for this additional step is a modified butt-contact mask, comprising enlarging the conventional butt-contact opening by between about 0.005 μm and 0.2 μm, an effect that can also be achieved by photo over-expose. This modified butt-contact mask exposes a spacer that is adjacent to the butt-contact hole, this spacer is removed. S/D impurity implant is performed after which conventional processing steps are applied for completion of the multi-transistor SRAM device.

摘要翻译： 为多晶体管SRAM器件创建了一种新的方法和结构。 遵循标准处理步骤，以创建提供栅极材料的图案化层，执行LDD杂质植入物的CMOS器件，产生栅极间隔物。 在形成栅极间隔物之后，添加光刻胶图案化和曝光的新步骤。 用于该附加步骤的掩模是改进的对接接触掩模，包括将常规对接接触开口扩大约0.005μm至0.2μm，这也可以通过曝光过度曝光实现。 该修改的对接接触掩模暴露与邻接孔相邻的间隔物，该间隔物被去除。 执行S / D杂质注入，之后应用传统的处理步骤来完成多晶体管SRAM器件。

公开(公告)号：US06979622B1

公开(公告)日：2005-12-27

申请号：US10924632

申请日：2004-08-24

申请人： Voon-Yew Thean ,  Dina H. Triyoso ,  Bich-Yen Nguyen

发明人： Voon-Yew Thean ,  Dina H. Triyoso ,  Bich-Yen Nguyen

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/165 ,  H01L29/51 ,  H01L21/366

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/165 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848

摘要： A transistor is formed using a semiconductor substrate and forming a control electrode overlying the semiconductor substrate. A first current electrode is formed within the semiconductor substrate and adjacent the control electrode. The first current electrode has a first predetermined semiconductor material. A second current electrode is formed within the semiconductor substrate and adjacent the control electrode to form a channel within the semiconductor substrate. The second current electrode has a second predetermined semiconductor material that is different from the first predetermined semiconductor material. The first predetermined semiconductor material is chosen to optimize bandgap energy of the first current electrode, and the second predetermined semiconductor material is chosen to optimize strain of the channel.

摘要翻译： 使用半导体衬底形成晶体管，并形成覆盖半导体衬底的控制电极。 第一电流电极形成在半导体衬底内并与控制电极相邻。 第一电流电极具有第一预定半导体材料。 第二电流电极形成在半导体衬底内并与控制电极相邻，以在半导体衬底内形成通道。 第二电流电极具有与第一预定半导体材料不同的第二预定半导体材料。 选择第一预定半导体材料以优化第一电流电极的带隙能量，并且选择第二预定半导体材料以优化通道的应变。

公开(公告)号：US06153451A

公开(公告)日：2000-11-28

申请号：US2977

申请日：1998-01-05

申请人： Louis N. Hutter ,  John P. Erdeljac ,  Jeffrey P. Smith

发明人： Louis N. Hutter ,  John P. Erdeljac ,  Jeffrey P. Smith

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L21/366

CPC分类号： H01L29/7816 ,  H01L29/66689 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/456

摘要： A method for increasing the operating voltage of a transistor formed on a substrate of a first conductivity region of a second conductivity type in a surface of the substrate. An N-well adjust region of the first conductivity type is then formed in the N-well region. The N-well adjust region extends to a first depth in the N-well region. A double diffusion well of the first conductivity type is then formed in the N-well. The double diffusion well extends to a second depth greater than the first depth of the N-well adjust region, and contains a portion of the N-well. Two N- channel stop regions are then formed in the N-well. The two N-channel stop regions extending to a third depth greater than the depth of the N-well adjust region, and contain a portion of the N-well.

摘要翻译： 一种在衬底的表面中增加形成在第二导电类型的第一导电区域的衬底上的晶体管的工作电压的方法。 然后在N阱区域中形成第一导电类型的N阱调节区域。 N阱调整区域延伸到N阱区域中的第一深度。 然后在N阱中形成第一导电类型的双扩散阱。 双扩散阱延伸到大于N阱调节区域的第一深度的第二深度，并且包含N阱的一部分。 然后在N阱中形成两个N-通道停止区。 两个N沟道停止区延伸到大于N阱调整区的深度的第三深度，并且包含N阱的一部分。

公开(公告)号：US07732289B2

公开(公告)日：2010-06-08

申请号：US11174683

申请日：2005-07-05

申请人： Chii-Ming Wu ,  Chih-Wei Chang ,  Pang-Yen Tsai ,  Chih-Chien Chang

发明人： Chii-Ming Wu ,  Chih-Wei Chang ,  Pang-Yen Tsai ,  Chih-Chien Chang

IPC分类号： H01L21/366

CPC分类号： H01L29/665 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7843

摘要： A method of forming MOS devices is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode over the gate dielectric, forming a source/drain region in the semiconductor substrate, forming an additional layer, preferably by epitaxial growth, on the source/drain region, and siliciding at least a top portion of the additional layer. The additional layer compensates for at least a portion of the semiconductor material lost during manufacturing processes and increases the distance between the source/drain silicide and the substrate. As a result, the leakage current is reduced. A transistor formed using the preferred embodiment preferably includes a silicide over the gate electrode wherein the silicide extends beyond a sidewall boundary of the gate electrode.

摘要翻译： 提供了一种形成MOS器件的方法。 该方法包括提供半导体衬底，在半导体衬底上形成栅极电介质，在栅极电介质上形成栅电极，在半导体衬底中形成源/漏区，在源上形成附加层，优选通过外延生长 /漏极区域，并且至少将附加层的顶部部分硅化。 附加层补偿在制造过程中损失的半导体材料的至少一部分，并且增加源极/漏极硅化物和衬底之间的距离。 结果，泄漏电流降低。 使用优选实施例形成的晶体管优选地包括在栅极上的硅化物，其中硅化物延伸超过栅电极的侧壁边界。

公开(公告)号：US07041557B2

公开(公告)日：2006-05-09

申请号：US10832952

申请日：2004-04-27

申请人： Sung-Taeg Kang ,  Jeong-Uk Han ,  Sung-Woo Park ,  Seung-Beom Yoon ,  Ji-Hoon Park ,  Bo-Young Seo

发明人： Sung-Taeg Kang ,  Jeong-Uk Han ,  Sung-Woo Park ,  Seung-Beom Yoon ,  Ji-Hoon Park ,  Bo-Young Seo

IPC分类号： H01L21/366

CPC分类号： H01L21/0214 ,  H01L21/02249 ,  H01L21/02252 ,  H01L21/28273 ,  H01L21/3144

摘要： In a method for forming a semiconductor device and a semiconductor device formed in accordance with the method, a thin dielectric layer is provided between a lower conductive layer and an upper conductive layer. In one embodiment, the thin dielectric layer comprises an inter-gate dielectric layer, the lower conductive layer comprises a floating gate and the upper dielectric layer comprises a control gate of a transistor, for example, a non-volatile memory cell transistor. The thin dielectric layer is formed using a heat treating process that results in reduction of surface roughness of the underlying floating gate, and results in a thin silicon oxy-nitride layer being formed on the floating gate. In this manner, the thin dielectric layer provides for increased capacitive coupling between the lower floating gate and the upper control gate. This also leads to a lowered programming voltage, erasing voltage and read voltage for the transistor, while maintaining the threshold voltage in a desired range. In addition, the size of the transistor and resulting storage cell can be minimized and the need for a high-voltage region in the circuit is mitigated, since, assuming a lowered programming voltage, pumping circuitry is not required.

摘要翻译： 在根据该方法形成的半导体器件和半导体器件的形成方法中，在下导电层和上导电层之间设置有薄的电介质层。 在一个实施例中，薄介电层包括栅极间电介质层，下导电层包括浮动栅极，上介电层包括晶体管的控制栅极，例如非易失性存储单元晶体管。 使用导致下面的浮置栅极的表面粗糙度降低的热处理工艺形成薄介电层，并且导致在浮动栅极上形成薄的氧氮化硅层。 以这种方式，薄介电层提供在下浮动栅极和上控制栅极之间增加的电容耦合。 这也导致降低的编程电压，擦除晶体管的电压和读取电压，同时将阈值电压保持在期望的范围内。 此外，晶体管和所得到的存储单元的尺寸可以被最小化，并且减轻了对电路中的高电压区域的需要，因为假设降低的编程电压，不需要泵浦电路。