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    Multi-layered, integrated circuit package having reduced parasitic noise characteristics
    2.
    发明授权
    Multi-layered, integrated circuit package having reduced parasitic noise characteristics 失效
    具有降低的寄生噪声特性的多层集成电路封装

    公开(公告)号：US5625225A

    公开(公告)日：1997-04-29

    申请号：US589751

    申请日：1996-01-22

    申请人： Chin-Ching Huang ,  Sang S. Lee ,  Ramachandra A. Rao ,  Fernand N. Forcier, Jr.

    发明人： Chin-Ching Huang ,  Sang S. Lee ,  Ramachandra A. Rao ,  Fernand N. Forcier, Jr.

    IPC分类号： H01L23/055 ,  H01L23/498 ,  H01L23/50 ,  H01L23/64 ,  H01L23/053

    CPC分类号： H01L23/49822 ,  H01L23/055 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/642 ,  H01L24/49 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/3011

    摘要： A multi-layered, high performance integrated circuit package is disclosed having a number of design features which increase the performance and manufacturability of the integrated circuit package, and reduce the effects of parasitic noise generated within the package. The metallic layers connecting contact fingers formed on ledges around the periphery of a die cavity area, to their respective package pins are organized such that a ground metallic layer is interposed between each pair of input/output signal metallic layers, and each input/output signal metallic layer is sandwiched between a pair of metallic layers wherein one layer of the pair is connected to a voltage supply and the other layer of the pair is connected to a corresponding ground reference. On one of the ledges, contact fingers corresponding to a first set of input/output signals are evenly dispersed around contact fingers corresponding to the ground reference, and on another one of the ledges, contact fingers corresponding to a second set of input/output signals are evenly dispersed around contact fingers corresponding to the voltage supply. On a bottom surface of the integrated circuit package a plurality of pins are arranged in a pin-grid-array, and pins corresponding to the voltage supply and ground reference are placed in the four outer corners of the bottom surface, so as to minimize parasitic noise generated on the voltage and ground lines connected to these pins, by active circuitry of the packaged integrated circuit.

    摘要翻译： 公开了一种多层，高性能的集成电路封装，其具有提高集成电路封装的性能和可制造性的许多设计特征，并且减少了在封装内产生的寄生噪声的影响。 将形成在模腔区域的周边的凸缘上形成的接触指状物的金属层组装成各自的封装引脚，使得接地金属层插入在每对输入/输出信号金属层之间，并且每个输入/输出信号 金属层夹在一对金属层之间，其中一对的一个层连接到电压源，另一层连接到相应的接地参考。 在一个凸缘上，与第一组输入/输出信号相对应的接触指针被均匀地分散在对应于接地基准的接触手指周围，并且在另一个凸缘上，接触指针对应于第二组输入/输出信号 均匀地分散在对应于电压源的接触手指周围。 在集成电路封装的底表面上，多个引脚布置成pin栅格阵列，并且对应于电压源和接地参考的引脚被放置在底表面的四个外角中，以便最小化寄生 通过封装集成电路的有源电路在连接到这些引脚的电压和地线上产生噪声。

    Current mode logic circuit
    3.
    发明授权
    Current mode logic circuit 失效
    电流模式逻辑电路

    公开(公告)号：US3942033A

    公开(公告)日：1976-03-02

    申请号：US466116

    申请日：1974-05-02

    申请人： Frank J. Swiatowiec ,  Ramachandra A. Rao

    发明人： Frank J. Swiatowiec ,  Ramachandra A. Rao

    IPC分类号： H03K19/086 ,  H03K17/00

    CPC分类号： H03K19/086

    摘要： A current mode logic circuit providing AND/OR type functions wherein "0" voltage level changes and spikes are substantially eliminated without sacrificing switching speeds by omitting conventional emitter and collector-dotting between the logic input gates and an emitter-follower output stage. The input gates employ diode loads for generating reduced signal swings for driving the output gate. The output gate contains more devices than a single emitter-follower output stage, but the reduced signal swing and a push-pull drive mode for the output gate offsets any increased switching times due to the greater number of devices and thus achieves the overall objectives without any overall sacrifice in switching speed.

    摘要翻译： 提供AND / OR型功能的电流模式逻辑电路，其中通过省略逻辑输入门和发射极 - 跟随器输出级之间的常规发射极和集电极点，基本上消除了“0”电压电平变化和尖峰，而不牺牲开关速度。 输入门采用二极管负载来产生用于驱动输出门的减小的信号摆幅。 输出门包含比单个射极跟随器输出级更多的器件，但减少的信号摆幅和输出栅极的推挽驱动模式可以抵消任何增加的开关时间，这是由于器件数量较多，从而实现了整体目标， 任何总体牺牲切换速度。

    High band width emitter coupled logic gate
    4.
    发明授权
    High band width emitter coupled logic gate 失效
    高带宽发射器耦合逻辑门

    公开(公告)号：US3978347A

    公开(公告)日：1976-08-31

    申请号：US511327

    申请日：1974-10-02

    申请人： Roger L. Hollstein ,  Ramachandra A. Rao

    发明人： Roger L. Hollstein ,  Ramachandra A. Rao

    IPC分类号： H03K19/013 ,  H03K19/086 ,  H03K19/08 ,  H03K5/01

    CPC分类号： H03K19/086 ,  H03K19/0136

    摘要： A high band width logic gate including a basic current switch logic block and emitter-follower output transistors. A switchable active circuit current sink is connected between an internal voltage switching node associated with the current switch logic gate and the emitter terminal of the emitter-follower output transistor. The active current sink is switched between a relatively low conductive state to a relatively high nonsaturating conductive state in order to maintain substantially constant current flow through the emitter-follower output transistor during switching of the logic gate in order to significantly improve AC beta roll off characteristics.