公开(公告)号：US08860150B2

公开(公告)日：2014-10-14

申请号：US12634689

申请日：2009-12-10

申请人： Chin-Fu Lin ,  Nien-Ting Ho ,  Chun-Hsien Lin ,  Chih-Hao Yu ,  Cheng-Hsien Chou

发明人： Chin-Fu Lin ,  Nien-Ting Ho ,  Chun-Hsien Lin ,  Chih-Hao Yu ,  Cheng-Hsien Chou

IPC分类号： H01L21/70 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/49

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： The metal gate structure of the present invention can include a TiN complex, and the N/Ti proportion of the TiN complex is decreased from bottom to top. In one embodiment, the TiN complex can include a single TiN layer, which has an N/Ti proportion gradually decreasing from bottom to top. In another embodiment, the TiN complex can include a plurality of TiN layers stacking together. In such a case, the lowest TiN layer has a higher N/Ti proportion than the adjusted TiN layer.

摘要翻译： 本发明的金属栅极结构可以包括TiN络合物，TiN络合物的N / Ti比例从下到上减小。 在一个实施方案中，TiN络合物可以包括单个TiN层，其具有从底部到顶部逐渐减小的N / Ti比例。 在另一个实施方案中，TiN复合物可以包括堆叠在一起的多个TiN层。 在这种情况下，最低的TiN层具有比调整后的TiN层更高的N / Ti比例。

公开(公告)号：US20110140207A1

公开(公告)日：2011-06-16

申请号：US12634689

申请日：2009-12-10

申请人： Chin-Fu Lin ,  Nien-Ting Ho ,  Chun-Hsien Lin ,  Chih-Hao Yu ,  Cheng-Hsien Chou

发明人： Chin-Fu Lin ,  Nien-Ting Ho ,  Chun-Hsien Lin ,  Chih-Hao Yu ,  Cheng-Hsien Chou

IPC分类号： H01L29/49 ,  H01L21/28

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： The metal gate structure of the present invention can include a TiN complex, and the N/Ti proportion of the TiN complex is decreased from bottom to top. In one embodiment, the TiN complex can include a single TiN layer, which has an N/Ti proportion gradually decreasing from bottom to top. In another embodiment, the TiN complex can include a plurality of TiN layers stacking together. In such a case, the lowest TiN layer has a higher N/Ti proportion than the adjusted TiN layer.

摘要翻译： 本发明的金属栅极结构可以包括TiN络合物，TiN络合物的N / Ti比例从下到上减小。 在一个实施方案中，TiN络合物可以包括单个TiN层，其具有从底部到顶部逐渐减小的N / Ti比例。 在另一个实施方案中，TiN复合物可以包括堆叠在一起的多个TiN层。 在这种情况下，最低的TiN层具有比调整后的TiN层更高的N / Ti比例。

公开(公告)号：US08404535B2

公开(公告)日：2013-03-26

申请号：US13304409

申请日：2011-11-25

申请人： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Cheng-Hsien Chou ,  Tian-Fu Chiang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Guang-Hwa Ma

发明人： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Cheng-Hsien Chou ,  Tian-Fu Chiang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC分类号： H01L21/28

CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.

摘要翻译： 公开了一种用于制造金属栅极晶体管的方法。 首先，提供具有第一晶体管区域和第二晶体管区域的衬底。 接下来，在基板上形成层叠膜，其中层叠膜包括至少一个高k电介质层和第一金属层。 图案化层叠的膜以在第一晶体管区域和第二晶体管区域中形成多个栅极，在栅极上形成电介质层，并且介电层的一部分被平坦化，直到到达每个栅极的顶部。 第一金属层从第二晶体管区域的栅极去除，并且第二金属层形成在电介质层的表面上，每个栅极用于在第一晶体管区域和第二晶体管区域中形成多个金属栅极。

公开(公告)号：US08193050B2

公开(公告)日：2012-06-05

申请号：US12907016

申请日：2010-10-18

申请人： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

发明人： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC分类号： H01L21/8238

CPC分类号： H01L27/11

摘要： A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.

摘要翻译： 公开了一种制造半导体结构的方法。 提供具有第一晶体管的衬底，其具有第一虚拟栅极和具有第二虚拟栅极的第二晶体管。 第一晶体管和第二晶体管的导电类型不同。 同时去除第一和第二伪栅极以形成相应的第一和第二开口。 在基板上形成高k电介质层，第二导电层和第一低电阻导电层，并填充第一和第二开口，第一低电阻导电层填充第二开口。 第一开口中的第一低电阻导电层和第二导电层被去除。 然后在第一开口中形成第一导电层和第二低电阻导电层，第二低电阻导电层填充第一开口。

公开(公告)号：US20110034019A1

公开(公告)日：2011-02-10

申请号：US12907016

申请日：2010-10-18

申请人： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

发明人： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC分类号： H01L21/28

CPC分类号： H01L27/11

摘要： A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.

摘要翻译： 公开了一种制造半导体结构的方法。 提供具有第一晶体管的衬底，其具有第一虚拟栅极和具有第二虚拟栅极的第二晶体管。 第一晶体管和第二晶体管的导电类型不同。 同时去除第一和第二伪栅极以形成相应的第一和第二开口。 在基板上形成高k电介质层，第二导电层和第一低电阻导电层，并填充第一和第二开口，第一低电阻导电层填充第二开口。 第一开口中的第一低电阻导电层和第二导电层被去除。 然后在第一开口中形成第一导电层和第二低电阻导电层，第二低电阻导电层填充第一开口。

公开(公告)号：US20110031558A1

公开(公告)日：2011-02-10

申请号：US12907036

申请日：2010-10-19

申请人： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

发明人： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC分类号： H01L27/11

CPC分类号： H01L27/11

摘要： A gate structure of a semiconductor device includes a first low resistance conductive layer, a second low resistance conductive layer, and a first type conductive layer disposed between and directly contacting sidewalls of the first low resistance conductive layer and the second low resistance conductive layer.

摘要翻译： 半导体器件的栅极结构包括第一低电阻导电层，第二低电阻导电层和设置在第一低电阻导电层和第二低电阻导电层的侧壁之间且直接接触的第一类型导电层。

公开(公告)号：US07838946B2

公开(公告)日：2010-11-23

申请号：US12058208

申请日：2008-03-28

申请人： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

发明人： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC分类号： H01L29/76

CPC分类号： H01L27/11

摘要： A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.

摘要翻译： 公开了一种制造半导体结构的方法。 提供具有第一晶体管的衬底，其具有第一虚拟栅极和具有第二虚拟栅极的第二晶体管。 第一晶体管和第二晶体管的导电类型不同。 同时去除第一和第二伪栅极以形成相应的第一和第二开口。 在基板上形成高k电介质层，第二导电层和第一低电阻导电层，并填充第一和第二开口，第一低电阻导电层填充第二开口。 第一开口中的第一低电阻导电层和第二导电层被去除。 然后在第一开口中形成第一导电层和第二低电阻导电层，第二低电阻导电层填满第一开口。

公开(公告)号：US08816439B2

公开(公告)日：2014-08-26

申请号：US12907036

申请日：2010-10-19

申请人： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

发明人： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC分类号： H01L29/76 ,  H01L27/11

CPC分类号： H01L27/11

摘要： A gate structure of a semiconductor device includes a first low resistance conductive layer, a second low resistance conductive layer, and a first type conductive layer disposed between and directly contacting sidewalls of the first low resistance conductive layer and the second low resistance conductive layer.

摘要翻译： 半导体器件的栅极结构包括第一低电阻导电层，第二低电阻导电层和设置在第一低电阻导电层和第二低电阻导电层的侧壁之间且直接接触的第一类型导电层。

公开(公告)号：US07799630B2

公开(公告)日：2010-09-21

申请号：US12018214

申请日：2008-01-23

申请人： Chih-Hao Yu ,  Li-Wei Cheng ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ting Lin ,  Che-Hua Hsu ,  Guang-Hwa Ma

发明人： Chih-Hao Yu ,  Li-Wei Cheng ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ting Lin ,  Che-Hua Hsu ,  Guang-Hwa Ma

IPC分类号： H01L21/8238

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

摘要： A method for manufacturing a CMOS device having dual metal gate includes providing a substrate having at least two transistors of different conductive types and a dielectric layer covering the two transistors, planarizing the dielectric layer to expose gate conductive layers of the two transistors, forming a patterned blocking layer exposing one of the conductive type transistor, performing a first etching process to remove a portion of a gate of the conductive type transistor, reforming a metal gate, removing the patterned blocking layer, performing a second etching process to remove a portion of a gate of the other conductive type transistor, and reforming a metal gate.

摘要翻译： 一种用于制造具有双金属栅极的CMOS器件的方法包括：提供具有不同导电类型的至少两个晶体管的衬底和覆盖两个晶体管的电介质层，平坦化介电层以暴露两个晶体管的栅极导电层，形成图案化 阻挡层暴露导电型晶体管之一，执行第一蚀刻工艺以去除导电型晶体管的栅极的一部分，重整金属栅极，去除图案化阻挡层，执行第二蚀刻工艺以去除部分 另一导电型晶体管的栅极，以及金属栅极的重整。

公开(公告)号：US20100059833A1

公开(公告)日：2010-03-11

申请号：US12208352

申请日：2008-09-11

申请人： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Cheng-Hsien Chou ,  Tian-Fu Chiang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Guang-Hwa Ma

发明人： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Cheng-Hsien Chou ,  Tian-Fu Chiang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC分类号： H01L47/00 ,  H01L21/8236

CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.

摘要翻译： 公开了一种用于制造金属栅极晶体管的方法。 首先，提供具有第一晶体管区域和第二晶体管区域的衬底。 接下来，在基板上形成层叠膜，其中层叠膜包括至少一个高k电介质层和第一金属层。 图案化层叠的膜以在第一晶体管区域和第二晶体管区域中形成多个栅极，在栅极上形成电介质层，并且介电层的一部分被平坦化，直到到达每个栅极的顶部。 第一金属层从第二晶体管区域的栅极去除，并且第二金属层形成在电介质层的表面上，每个栅极用于在第一晶体管区域和第二晶体管区域中形成多个金属栅极。