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公开(公告)号：US11121677B1
公开(公告)日：2021-09-14
申请号：US16625671
申请日：2016-01-26
发明人： Daiguo Xu , Gangyi Hu , Ruzhang Li , Jian'an Wang , Guangbing Chen , Yuxin Wang , Tao Liu , Lu Liu , Minming Deng , Hanfu Shi , Xu Wang
摘要： Provided in the present invention is a transconductance amplifier based on a self-biased cascode structure. The transconductance amplifier includes a self-biased cascode input-stage structure constituted by PMOS (P-channel Metal Oxide Semiconductor) input transistors M1, M2, M3 and M4, a self-biased cascode first-stage load structure constituted by NMOS (N-channel Metal Oxide Semiconductor) transistors M5, M6, M7 and M8, a second-stage common-source amplifier structure constituted by an NMOS transistor M9 and a PMOS transistor M10, a bias circuit structure constituted by NMOS transistors M11 and M12 and a PMOS transistor M13, an amplifier compensation capacitor Cc, an amplifier load capacitor CL, a reference current source Iref and a PMOS transistor M0 that provides a constant current source function. Further provided in the present invention is a transconductance amplifier based on a self-biased cascode structure, which adopts an NMOS transistor as an input transistor. Both input transistors and load transistors of a first-stage amplifier of the present invention adopt self-biased cascode structures, such that the output impedance and the DC gain of the first-stage amplifier are increased. Substrate voltages of the MOS transistors of the first-stage amplifier are provided by an amplifier bias circuit. Owing to a connection mode of the compensation capacitor Cc, a higher figure of merit is achieved.
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公开(公告)号：US10003352B2
公开(公告)日：2018-06-19
申请号：US15559055
申请日：2015-06-08
发明人： Ting Li , Gangyi Hu , Hequan Jiang , Ruzhang Li , Zhengbo Huang , Yong Zhang , Guangbing Chen , Yuxin Wang , Dongbing Fu
CPC分类号： H03M1/468 , H03M1/0678 , H03M1/1061 , H03M1/1245 , H03M1/42 , H03M1/804
摘要： The present invention provides a high-precision analog-to-digital converter, includes a redundant weight capacitor array, a comparator, a code reestablishment circuit, a weight storage circuit and a control logic circuit. The redundant weight capacitor array collects input voltages and generates output voltages in a sampling stage. The comparator compares the output voltages of the redundant weight capacitor array. The code reestablishment circuit calculates an output code of the successive approximation type analog-to-digital converter according to the comparator output result and a capacitor weight in the weight storage circuit. The weight storage circuit stores the capacitor weight. The control logic circuit controls the sampling and conversion stages of the redundant weight capacitor array. The present invention also provides a DNL-based performance improvement method adapted to the analog-to-digital converter.
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公开(公告)号：US10181821B2
公开(公告)日：2019-01-15
申请号：US15555543
申请日：2016-01-26
发明人： Daiguo Xu , Gangyi Hu , Ruzhang Li , Jian'an Wang , Guangbing Chen , Yuxin Wang , Tao Liu , Lu Liu , Minming Deng , Hanfu Shi , Xu Wang
摘要： The present invention provides a frequency-compensated transconductance amplifier, includes an input stage consisting of NMOS transistors M1 and M2, a first-stage active load consisting of PMOS transistors M3 and M4, a first-stage tail current source consisting of a constant current source Iss, a second-stage input transistor consisting of a PMOS transistor M5, a second-stage constant current source consisting of an NMOS transistor M6, a load capacitor consisting of a capacitor CL, and a frequency compensation network formed by sequentially connecting a gain stage GAIN, a compensating resistor Rc and a compensating capacitor Cc in series.
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