公开(公告)号：US09667267B2

公开(公告)日：2017-05-30

申请号：US15121381

申请日：2015-01-28

申请人： China Electronic Technology Corporation, 24th Research Institute

发明人： Yan Wang ,  Gang-Yi Hu ,  Tao Liu ,  Yu-Xin Wang ,  Jian-An Wang ,  Dong-Bing Fu ,  Ting Li ,  Guang-Bing Chen

IPC分类号： H03M1/20 ,  H03M1/10 ,  H03M1/12 ,  H03M1/46 ,  H03M1/06 ,  H03M1/74

CPC分类号： H03M1/201 ,  H03M1/0641 ,  H03M1/1009 ,  H03M1/1061 ,  H03M1/1245 ,  H03M1/46 ,  H03M1/742

摘要： A dither circuit for high-resolution analog-to-digital converters (ADCs) is presented, including a settable pseudorandom sequence generator, a trimming module, a trimmable digital-to-analog conversion circuit, a dither introduced circuit and a dither elimination circuit, wherein the settable pseudorandom sequence generator works to generate pseudorandom sequence signal uncorrelated to analog input signal and its output can be set, of which n bit output is taken as digital dither signal and n can be less than the quantization bit of the ADC; the trimming module works to determine the trimming signals for the trimmable digital-to-analog conversion circuit to convert the digital dither signal into analog dither signal precisely; the dither introduced circuit works to introduce the analog dither signal to the ADC; the dither elimination circuit works to remove the digital dither signal from the output of ADC. The dither circuit features less complexity and better dynamic performance for high-resolution ADC.

公开(公告)号：US11121677B1

公开(公告)日：2021-09-14

申请号：US16625671

申请日：2016-01-26

申请人： CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE

发明人： Daiguo Xu ,  Gangyi Hu ,  Ruzhang Li ,  Jian'an Wang ,  Guangbing Chen ,  Yuxin Wang ,  Tao Liu ,  Lu Liu ,  Minming Deng ,  Hanfu Shi ,  Xu Wang

IPC分类号： H03F3/45 ,  H03F1/22

摘要： Provided in the present invention is a transconductance amplifier based on a self-biased cascode structure. The transconductance amplifier includes a self-biased cascode input-stage structure constituted by PMOS (P-channel Metal Oxide Semiconductor) input transistors M1, M2, M3 and M4, a self-biased cascode first-stage load structure constituted by NMOS (N-channel Metal Oxide Semiconductor) transistors M5, M6, M7 and M8, a second-stage common-source amplifier structure constituted by an NMOS transistor M9 and a PMOS transistor M10, a bias circuit structure constituted by NMOS transistors M11 and M12 and a PMOS transistor M13, an amplifier compensation capacitor Cc, an amplifier load capacitor CL, a reference current source Iref and a PMOS transistor M0 that provides a constant current source function. Further provided in the present invention is a transconductance amplifier based on a self-biased cascode structure, which adopts an NMOS transistor as an input transistor. Both input transistors and load transistors of a first-stage amplifier of the present invention adopt self-biased cascode structures, such that the output impedance and the DC gain of the first-stage amplifier are increased. Substrate voltages of the MOS transistors of the first-stage amplifier are provided by an amplifier bias circuit. Owing to a connection mode of the compensation capacitor Cc, a higher figure of merit is achieved.

公开(公告)号：US10971929B2

公开(公告)日：2021-04-06

申请号：US16310451

申请日：2016-06-22

申请人： CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE

发明人： Yan Wang ,  Tao Liu ,  Guang-Bing Chen ,  Yu-Xin Wang ,  Dong-Bing Fu ,  Yu-Jun Yang ,  Liang Chen ,  Yang Pu

IPC分类号： H02H9/04 ,  H01L27/02 ,  H01L23/522 ,  H02H9/00 ,  H05F3/02 ,  H01L23/00

摘要： The present invention provides a chip ESD protection circuit, includes an integrated circuit layer and a conductive layer. A first ground bonding pad that is connected to a first ground wire of a first power domain is disposed on each of the first power domain and a second power domain in the integrated circuit layer. The first ground bonding pads are bonded to the conductive layer. A second power clamping unit is disposed on the second power domain. A first end of the second power clamping unit is connected to a second power wire of the second power domain, and a second end thereof is connected to the first ground wire or a second ground wire of the second power domain. According to the chip ESD protection circuit, the ESD protection capability of a chip can be improved. The occupied area of the chip is reduced.

公开(公告)号：US10666243B2

公开(公告)日：2020-05-26

申请号：US16475123

申请日：2016-07-07

申请人： CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE

发明人： Dai-Guo Xu ,  Gang-Yi Hu ,  Ru-Zhang Li ,  Jian-An Wang ,  Guang-Bing Chen ,  Yu-Xin Wang ,  Dong-Bing Fu ,  Tao Liu

IPC分类号： H03K5/00 ,  H03K5/24 ,  H03K19/00 ,  H03K19/003

摘要： A high-speed low-power-consumption dynamic comparator includes a latch, an AND gate, a delay unit, and an XNOR gate. According to the high-speed low-power-consumption dynamic comparator, the output signal is generated through the XNOR gate from the comparator output signals Dp and Dn. The output signal and the control signal clk1 generate the control signal of the NMOS transistor P10 through the AND gate, so that the problem of static power consumption in a conventional comparator is solved.

公开(公告)号：US10181821B2

公开(公告)日：2019-01-15

申请号：US15555543

申请日：2016-01-26

申请人： China Electronic Technology Corporation, 24th Research Institute

发明人： Daiguo Xu ,  Gangyi Hu ,  Ruzhang Li ,  Jian'an Wang ,  Guangbing Chen ,  Yuxin Wang ,  Tao Liu ,  Lu Liu ,  Minming Deng ,  Hanfu Shi ,  Xu Wang

IPC分类号： H03F3/45 ,  H03F1/14

摘要： The present invention provides a frequency-compensated transconductance amplifier, includes an input stage consisting of NMOS transistors M1 and M2, a first-stage active load consisting of PMOS transistors M3 and M4, a first-stage tail current source consisting of a constant current source Iss, a second-stage input transistor consisting of a PMOS transistor M5, a second-stage constant current source consisting of an NMOS transistor M6, a load capacitor consisting of a capacitor CL, and a frequency compensation network formed by sequentially connecting a gain stage GAIN, a compensating resistor Rc and a compensating capacitor Cc in series.

公开(公告)号：US09336347B2

公开(公告)日：2016-05-10

申请号：US14396737

申请日：2013-11-28

申请人： China Electronic Technology Corporation, 24th Research Institute

发明人： Yan Wang ,  Yu-Xin Wang ,  Gang-Yi Hu ,  Ting Li ,  Tao Liu ,  Guang-Bing Chen

IPC分类号： H01G4/38 ,  G06F17/50 ,  H01G15/00 ,  H03M1/16 ,  H03M1/44

CPC分类号： G06F17/5072 ,  G06F17/50 ,  G06F17/5077 ,  H01G4/38 ,  H01G15/00 ,  H03M1/164 ,  H03M1/442

摘要： A layout design method is provided for generating capacitor arrays being described in four steps: first, the wiring mode of unit capacitors is defined allowing the wire being connected to the upper plate to parallel that to the lower one, second, a capacitor array layout is designed with capacitors being distributed in Mh lines, Mh is the maximum of capacitors' lines, the line numbers of Class 1 to Class K capacitors are defined in the unilateral capacitor array, third, the wiring mode is set for capacitor array making sure the lengths of the wires to the upper and lower plates of unit capacitors are equal, at last, parasitic parameters are characterized in ways that verify the layout. A capacitor array is provided as well. By eliminating capacitance mismatching caused by parasitic capacitance, the method works to generate a well-matched capacitor array in an easy and efficient way.

摘要翻译： 提供一种用于产生电容器阵列的布局设计方法，其分为四个步骤：首先，确定单元电容器的布线模式，允许将导线连接到上板与下板平行;第二，电容器阵列布局为 设计有电容分布在Mh线，Mh是电容器线的最大值，单相电容器阵列中定义了1类至K类电容器的线数;第三，为电容器阵列设置了布线模式，确保长度 到单元电容器的上板和下板的电线相等，最后，寄生参数以验证布局的方式进行表征。 还提供电容器阵列。 通过消除由寄生电容引起的电容失配，该方法可以以简单有效的方式产生良好匹配的电容器阵列。