公开(公告)号：US08723646B2

公开(公告)日：2014-05-13

申请号：US12210371

申请日：2008-09-15

申请人： Choongyeun Cho ,  Richard Ferri ,  Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim

发明人： Choongyeun Cho ,  Richard Ferri ,  Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim

IPC分类号： H04Q5/22

CPC分类号： H04Q9/00 ,  H04Q2209/47

摘要： An identification method and identification device are presented employing radio frequency and acoustic wave communication modes. The identification method includes: receiving at an acoustic wave and radio frequency identification device an acoustic wave signal of a first frequency and a radio frequency signal of a second frequency, where the acoustic wave signal and the radio frequency signal are received from an acoustic wave and radio frequency identification reader, and the first frequency and the second frequency are different frequencies; and responding to the receiving by transmitting at least one of an acoustic wave identification (AWID) or a radio frequency identification (RFID) from the acoustic wave and radio frequency identification device.

摘要翻译： 采用射频和声波通信方式提出了识别方法和识别装置。 识别方法包括：在声波和射频识别装置处接收第一频率的声波信号和从声波接收声波信号和射频信号的第二频率的射频信号， 射频识别读取器，第一频率和第二频率是不同的频率; 以及通过从声波和射频识别装置发送声波识别（AWID）或射频识别（RFID）中的至少一个来响应于接收。

公开(公告)号：US07902880B2

公开(公告)日：2011-03-08

申请号：US12844339

申请日：2010-07-27

申请人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim

发明人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim

IPC分类号： H01L25/00 ,  H03K19/00

CPC分类号： H03K19/0016 ,  Y10T29/49002

摘要： Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more p-type wells in the semiconductor substrate, multiple p-channel transistors disposed at least partially in one or more n-type wells in the semiconductor substrate, and a backgate control circuit. The backgate control circuit is electrically coupled to the p-type well(s) and to the n-type well(s) to facilitate transitioning of the multiple n-channel transistors and the multiple p-channel transistors from backgate biased standby mode to active mode by automatically shunting charge from the n-type well(s) to the p-type well(s) until a well voltage threshold is reached indicative of a completed transition of the transistors from backgate biased standby mode to active mode.

摘要翻译： 提供了电路和方法，以便于将数字电路从背栅极偏置待机模式转换到主动模式。 数字电路包括半导体衬底，至少部分地设置在半导体衬底中的一个或多个p型阱中的多个n沟道晶体管，至少部分地设置在半导体中的一个或多个n型阱中的多个p沟道晶体管 基板和背栅控制电路。 背栅控制电路电耦合到p型阱和n型阱，以便于将多个n沟道晶体管和多个p沟道晶体管从背栅极偏置待机模式转换到有源 模式，通过自动将电荷从n型阱转移到p型阱，直到达到阱电压阈值，表明晶体管从背栅极偏置待机模式到活动模式的完成转变。

公开(公告)号：US08273648B2

公开(公告)日：2012-09-25

申请号：US13369592

申请日：2012-02-09

申请人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim ,  James R. Moulic

发明人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim ,  James R. Moulic

IPC分类号： H01L21/3205

CPC分类号： H01L23/5225 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/00

摘要： Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the circuit structure and include at least one vertically-extending conductive pattern disposed adjacent to the edge of the circuit structure. The vertically-extending conductive pattern is defined, at least partially, by a plurality of elements disposed in the multiple BEOL layers. The plurality of elements are uniformly arrayed at the edge of the circuit structure in a first direction or a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in the first direction or the second direction to block electromagnetic interference of a particular wavelength from passing therethrough.

公开(公告)号：US07791403B2

公开(公告)日：2010-09-07

申请号：US12206124

申请日：2008-09-08

申请人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim

发明人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： H03K19/0016 ,  Y10T29/49002

摘要： Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more p-type wells in the semiconductor substrate, multiple p-channel transistors disposed at least partially in one or more n-type wells in the semiconductor substrate, and a backgate control circuit. The backgate control circuit is electrically coupled to the p-type well(s) and to the n-type well(s) to facilitate transitioning of the multiple n-channel transistors and the multiple p-channel transistors from backgate biased standby mode to active mode by automatically shunting charge from the n-type well(s) to the p-type well(s) until a well voltage threshold is reached indicative of a completed transition of the transistors from backgate biased standby mode to active mode.

摘要翻译： 提供了电路和方法，以便于将数字电路从背栅极偏置待机模式转换到主动模式。 数字电路包括半导体衬底，至少部分地设置在半导体衬底中的一个或多个p型阱中的多个n沟道晶体管，至少部分地设置在半导体中的一个或多个n型阱中的多个p沟道晶体管 基板和背栅控制电路。 背栅控制电路电耦合到p型阱和n型阱，以便于将多个n沟道晶体管和多个p沟道晶体管从背栅极偏置待机模式转换到有源 模式，通过自动将电荷从n型阱转移到p型阱，直到达到阱电压阈值，表明晶体管从背栅极偏置待机模式到活动模式的完成转变。

公开(公告)号：US08138563B2

公开(公告)日：2012-03-20

申请号：US12188243

申请日：2008-08-08

申请人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim ,  James R. Moulic

发明人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim ,  James R. Moulic

IPC分类号： H01L29/82

CPC分类号： H01L23/5225 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/00

摘要： Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the circuit structure and include at least one vertically-extending conductive pattern disposed adjacent to the edge of the circuit structure. The vertically-extending conductive pattern is defined, at least partially, by a plurality of elements disposed in the multiple BEOL layers. The plurality of elements are uniformly arrayed at the edge of the circuit structure in a first direction or a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in the first direction or the second direction to block electromagnetic interference of a particular wavelength from passing therethrough.

摘要翻译： 提供了后端行（BEOL）电路结构和方法来阻止外部来源或内部产生的电磁边缘干扰。 一个这样的BEOL电路结构包括支撑一个或多个集成电路的半导体衬底和设置在半导体衬底上的多个BEOL层。 多个BEOL层延伸到电路结构的边缘并且包括邻近电路结构的边缘布置的至少一个垂直延伸的导电图案。 至少部分地由设置在多个BEOL层中的多个元件限定垂直延伸的导电图案。 多个元件在电路结构的边缘沿其第一方向或第二方向均匀地排列在其至少一部分上。 多个元件的大小和尺寸设置在第一方向或第二方向上，以阻止特定波长的电磁干扰通过。

公开(公告)号：US09013310B2

公开(公告)日：2015-04-21

申请号：US12178894

申请日：2008-07-24

申请人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim

发明人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim

IPC分类号： G08B13/14 ,  G06K19/077 ,  H01Q1/22 ,  H01Q1/24 ,  H01Q7/00 ,  H01Q23/00

CPC分类号： G06K19/07749 ,  H01Q1/2225 ,  H01Q1/248 ,  H01Q7/00 ,  H01Q23/00

摘要： A radio frequency identification (RFID) device and method of fabrication are presented. The RFID device includes an RFID antenna, a capacitor, and an RFID integrated circuit. The RFID antenna includes an elongate conductive trace disposed within an antenna area of the RFID device, and the capacitor includes an elongate capacitive structure for storing power. The elongate capacitive structure is aligned with the elongate conductive trace and embedded within the antenna area of the RFID device. The RFID integrated circuit is electrically coupled to the RFID antenna and to the capacitor, and the capacitor stores power within the antenna area of the RFID device to facilitate RFID integrated circuit functionality.

摘要翻译： 提出了射频识别（RFID）装置及其制造方法。 RFID设备包括RFID天线，电容器和RFID集成电路。 RFID天线包括设置在RFID设备的天线区域内的细长导电迹线，并且电容器包括用于存储电力的细长电容结构。 细长的电容结构与细长导电迹线对准，并且嵌入在RFID器件的天线区域内。 RFID集成电路电耦合到RFID天线和电容器，并且电容器在RFID设备的天线区域内存储功率以便于RFID集成电路功能。

公开(公告)号：US08148953B2

公开(公告)日：2012-04-03

申请号：US11946550

申请日：2007-11-28

申请人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim ,  James Randal Moulic

发明人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim ,  James Randal Moulic

IPC分类号： H02J7/00

CPC分类号： H02J7/345

摘要： An apparatus and method for recycling and reusing charge in an electronic circuit. The apparatus includes at least one capacitor coupled to a circuit block in the electronic circuit, the capacitor being configured to collect current charge consumed by the circuit block when set to a charge collection mode, and a voltage level comparator configured to detect a fully charged state when the capacitor is fully charged. Further, the apparatus includes a first electrical switch configured to allow, once the fully charged state is detected, the capacitor to switch to a discharge mode for discharging the current charge collected back into the power supply for reuse by the electrical system and a second switch configured to allow, after the capacitor has fully discharged the current charge collected, the capacitor to switch back to the charge collection mode, such that, the current charge is recycled and reused by the electrical system.

摘要翻译： 一种用于在电子电路中再循环和再利用电荷的装置和方法。 该装置包括耦合到电子电路中的电路块的至少一个电容器，电容器被配置为当设置为电荷收集模式时收集由电路块消耗的当前电荷;以及电压电平比较器，被配置为检测完全充电状态 当电容器充满电时。 此外，该装置包括第一电开关，其被配置为允许一旦检测到完全充电状态，电容器切换到放电模式，用于将收集的当前电荷放回电源供电系统和第二开关 配置为允许在电容器已经完全放电所收集的当前电荷之后，电容器切换回电荷收集模式，使得当前电荷被电气系统再循环和再利用。

公开(公告)号：US07821110B2

公开(公告)日：2010-10-26

申请号：US11747342

申请日：2007-05-11

申请人： Dae Ik Kim ,  Jonghae Kim ,  Moon Ju Kim ,  Choongyeun Cho

发明人： Dae Ik Kim ,  Jonghae Kim ,  Moon Ju Kim ,  Choongyeun Cho

IPC分类号： H01L23/552

CPC分类号： H01L23/552 ,  H01L2924/0002 ,  H01L2924/00

摘要： Back end of line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic interference. One such BEOL circuit structure includes one or more semiconductor substrates supporting one or more integrated circuits, and one or more BEOL layers disposed over the semiconductor substrate(s). At least one BEOL layer includes a conductive pattern defined at least partially by a plurality of elements arrayed in a first direction and a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in at least one of the first and second directions to block electromagnetic interference of a particular wavelength from passing therethrough. In one implementation, a first conductive pattern of a first BEOL layer polarizes electromagnetic interference, and a second conductive pattern of a second BEOL layer blocks the polarized electromagnetic interference.

摘要翻译： 提供后端（BEOL）电路结构和方法来阻止外部来源或内部产生的电磁干扰。 一种这样的BEOL电路结构包括支撑一个或多个集成电路的一个或多个半导体衬底以及设置在半导体衬底之上的一个或多个BEOL层。 至少一个BEOL层包括至少部分地由在第一方向和第二方向排列的多个元件至少部分地限定的导电图案。 多个元件的大小和位置在第一和第二方向中的至少一个方向上，以阻止特定波长的电磁干扰通过。 在一个实施方案中，第一BEOL层的第一导电图案使电磁干扰偏振，并且第二BEOL层的第二导电图案阻挡极化的电磁干扰。

公开(公告)号：US07504705B2

公开(公告)日：2009-03-17

申请号：US11536896

申请日：2006-09-29

申请人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon J. Kim ,  Jean-Olivier Plouchart ,  Robert E. Trzcinski

发明人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon J. Kim ,  Jean-Olivier Plouchart ,  Robert E. Trzcinski

IPC分类号： G06F17/50

CPC分类号： H01L28/10 ,  H01F17/0013 ,  H01F2017/0073 ,  H01L23/5227 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.

摘要翻译： 提供了用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积 的设计规则检查规则。 对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。 在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。 在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化一个或多个芯片产量，芯片性能，芯片制造性和电感器Q因子参数。

公开(公告)号：US20120223411A1

公开(公告)日：2012-09-06

申请号：US13469464

申请日：2012-05-11

申请人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon J. Kim ,  Jean-Olivier Plouchart ,  Robert E. Trzcinski

发明人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon J. Kim ,  Jean-Olivier Plouchart ,  Robert E. Trzcinski

IPC分类号： H01L29/86 ,  H01L21/02

CPC分类号： H01L28/10 ,  H01F17/0013 ,  H01F2017/0073 ,  H01L23/5227 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.

摘要翻译： 提供了用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积 的设计规则检查规则。 对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。 在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。 在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化一个或多个芯片产量，芯片性能，芯片制造性和电感器Q因子参数。