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公开(公告)号：US08437442B2
公开(公告)日：2013-05-07
申请号：US12819910
申请日：2010-06-21
IPC分类号： H03D3/24
CPC分类号： H04L27/0014 , H04L2027/0018
摘要： A method and apparatus for generating a carrier frequency signal is disclosed. The method includes generating a first frequency signal; injecting a modulation signal at a first point of the two-point modulation architecture; generating a second frequency signal from the modulation signal; introducing the second frequency signal by mixing the first frequency signal and the second frequency signal to generate a mixed frequency signal and outputting the carrier frequency signal selected from the mixed frequency signal.
摘要翻译： 公开了一种用于产生载波频率信号的方法和装置。 该方法包括产生第一频率信号; 在所述两点调制架构的第一点处注入调制信号; 从所述调制信号产生第二频率信号; 通过混合第一频率信号和第二频率信号来引入第二频率信号以产生混合频率信号并输出从混合频率信号中选择的载波频率信号。
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公开(公告)号：US20110187424A1
公开(公告)日：2011-08-04
申请号：US13016089
申请日：2011-01-28
IPC分类号： H03L7/08
CPC分类号： H03L7/08
摘要： A method and a device for determining closed loop bandwidth characteristic of a Phase Locked Loop (PLL) (52) comprising a voltage controlled oscillator (VCO) (53) controlled by means of a tuning voltage (Vtune) is disclosed. An embodiment of the invention compares the VCO tuning voltage (Vtune) to a low threshold voltage (Vlow) and a high threshold voltage (Vhigh), creating an oscillation of the VCO tuning voltage by offsetting the divider value such that the PLL (52) forces the tuning voltage (Vtune) towards the high threshold voltage (Vhigh) when the low threshold voltage (Vlow) is reached, and offsetting the divider value such that said PLL (52) forces the tuning voltage (Vtune) towards the low threshold voltage (Vlow) when the high threshold voltage (Vhigh) is reached, measuring the period of the oscillation between the high and the low threshold voltage of the VCO tuning voltage by counting the number of cycles of a reference clock signal (clk), and comparing the number of reference clock cycles to a reference number of clock cycles to determine the relative loop bandwidth of the PLL (52).
摘要翻译： 公开了一种用于确定包括通过调谐电压（Vtune）控制的压控振荡器（VCO）53的锁相环（PLL）（52））的闭环带宽特性的方法和装置。 本发明的一个实施例将VCO调谐电压（Vtune）与低阈值电压（Vlow）和高阈值电压（Vhigh）进行比较，通过偏移分频器值来产生VCO调谐电压的振荡，使得PLL（52） 当达到低阈值电压（Vlow）时迫使调谐电压（Vtune）朝向高阈值电压（Vhigh），并且偏移分频器值，使得所述PLL（52）迫使调谐电压（Vtune）朝向低阈值电压 （Vhigh）时，通过对参考时钟信号（clk）的周期数进行计数来测量VCO调谐电压的高阈值电压和低阈值电压之间的振荡周期，并比较 参考时钟周期数到参考时钟周期数以确定PLL的相对环路带宽（52）。
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3.发明授权公开(公告)号：US08405434B2
公开(公告)日：2013-03-26
申请号：US13213579
申请日：2011-08-19
IPC分类号： H03L7/06
摘要： A Digital Calibration System for a Phase Locked Loop includes a Tuning Voltage Controller configured to set the tuning voltage to a value; a Phase Difference Quantizer configured to output a phase difference after comparing a phase of the reference signal with a phase of the feedback signal; a Digital Controller configured to receive the phase difference of the PDQ and control a coarse tuning signal such that an average phase difference of the PDQ is 0; and a Frequency Calibration Logic configured to calibrate the feedback signal in response to the output of the DC.
摘要翻译： 用于锁相环的数字校准系统包括调谐电压控制器，其被配置为将调谐电压设置为一个值; 相位差量化器，被配置为在将参考信号的相位与反馈信号的相位进行比较之后输出相位差; 数字控制器，被配置为接收PDQ的相位差并控制粗调谐信号，使得PDQ的平均相位差为0; 以及频率校准逻辑，被配置为响应于DC的输出来校准反馈信号。
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公开(公告)号：US08222961B2
公开(公告)日：2012-07-17
申请号：US13016089
申请日：2011-01-28
IPC分类号： H03L7/00
CPC分类号： H03L7/08
摘要： A method and a device for determining closed loop bandwidth characteristic of a Phase Locked Loop (PLL) (52) comprising a voltage controlled oscillator (VCO) (53) controlled by means of a tuning voltage (Vtune) is disclosed. An embodiment of the invention compares the VCO tuning voltage (Vtune) to a low threshold voltage (Vlow) and a high threshold voltage (Vhigh), creating an oscillation of the VCO tuning voltage by offsetting the divider value such that the PLL (52) forces the tuning voltage (Vtune) towards the high threshold voltage (Vhigh) when the low threshold voltage (Vlow) is reached, and offsetting the divider value such that said PLL (52) forces the tuning voltage (Vtune) towards the low threshold voltage (Vlow) when the high threshold voltage (Vhigh) is reached, measuring the period of the oscillation between the high and the low threshold voltage of the VCO tuning voltage by counting the number of cycles of a reference clock signal (clk), and comparing the number of reference clock cycles to a reference number of clock cycles to determine the relative loop bandwidth of the PLL (52).
摘要翻译： 公开了一种用于确定包括通过调谐电压（Vtune）控制的压控振荡器（VCO）53的锁相环（PLL）（52））的闭环带宽特性的方法和装置。 本发明的一个实施例将VCO调谐电压（Vtune）与低阈值电压（Vlow）和高阈值电压（Vhigh）进行比较，通过偏移分频器值来产生VCO调谐电压的振荡，使得PLL（52） 当达到低阈值电压（Vlow）时迫使调谐电压（Vtune）朝向高阈值电压（Vhigh），并且偏移分频器值，使得所述PLL（52）迫使调谐电压（Vtune）朝向低阈值电压 （Vhigh）时，通过对参考时钟信号（clk）的周期数进行计数来测量VCO调谐电压的高阈值电压和低阈值电压之间的振荡周期，并比较 参考时钟周期数到参考时钟周期数以确定PLL的相对环路带宽（52）。
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5.发明申请公开(公告)号：US20110298507A1
公开(公告)日：2011-12-08
申请号：US13213579
申请日：2011-08-19
IPC分类号： H03L7/08
摘要： A Digital Calibration System for a Phase Locked Loop includes a Tuning Voltage Controller configured to set the tuning voltage to a value; a Phase Difference Quantizer configured to output a phase difference after comparing a phase of the reference signal with a phase of the feedback signal; a Digital Controller configured to receive the phase difference of the PDQ and control a coarse tuning signal such that an average phase difference of the PDQ is 0; and a Frequency Calibration Logic configured to calibrate the feedback signal in response to the output of the DC.
摘要翻译： 用于锁相环的数字校准系统包括调谐电压控制器，其被配置为将调谐电压设置为一个值; 相位差量化器，被配置为在将参考信号的相位与反馈信号的相位进行比较之后输出相位差; 数字控制器，被配置为接收PDQ的相位差并控制粗调谐信号，使得PDQ的平均相位差为0; 以及频率校准逻辑，被配置为响应于DC的输出来校准反馈信号。
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公开(公告)号：US20100329372A1
公开(公告)日：2010-12-30
申请号：US12819910
申请日：2010-06-21
CPC分类号： H04L27/0014 , H04L2027/0018
摘要： A method and apparatus for generating a carrier frequency signal is disclosed. The method includes generating a first frequency signal; injecting a modulation signal at a first point of the two-point modulation architecture; generating a second frequency signal from the modulation signal; introducing the second frequency signal by mixing the first frequency signal and the second frequency signal to generate a mixed frequency signal and outputting the carrier frequency signal selected from the mixed frequency signal.
摘要翻译： 公开了一种用于产生载波频率信号的方法和装置。 该方法包括产生第一频率信号; 在所述两点调制架构的第一点处注入调制信号; 从所述调制信号产生第二频率信号; 通过混合第一频率信号和第二频率信号来引入第二频率信号以产生混合频率信号并输出从混合频率信号中选择的载波频率信号。
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