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公开(公告)号：US20120059996A1
公开(公告)日：2012-03-08
申请号：US12876366
申请日：2010-09-07
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0811
摘要： A mechanism is provided for avoiding cross-interrogates for a streaming data optimized level one cache. The mechanism adds a set of dedicated registers, referred to as “copex registers,” to track ownership of the cache lines that the co-processor's L1 cache holds exclusive. The mechanism extends the cache directory of the L2 cache by a bit that identifies exclusive ownership of a cache line in the co-processor cache. The co-processor continuously provides an indication of which copex registers are valid. On any action that requires a directory lookup in the L2 cache, the mechanism compares the valid copex registers against the lookup address in parallel to the directory lookup. The mechanism considers the “exclusive ownership in co-processor” bit in the directory valid only if the cache line is also currently in a valid copex register.
摘要翻译： 提供了一种用于避免流数据优化的一级缓存的交叉询问的机制。 该机制添加了一组专用寄存器（称为“copex寄存器”）来跟踪协处理器的L1高速缓存保存的高速缓存行的所有权。 该机制将L2高速缓存的缓存目录扩展一个位，以识别协处理器高速缓存中高速缓存行的独占所有权。 协处理器连续提供哪些共享寄存器有效的指示。 对于需要在L2缓存中进行目录查找的任何操作，该机制将将有效的copex寄存器与查找地址并行地与目录查找进行比较。 该机制认为目录中的“独占所有权协同处理器”位只有当高速缓存行当前还在有效的copex寄存器中时才有效。
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2.发明授权公开(公告)号：US08495452B2
公开(公告)日：2013-07-23
申请号：US13024775
申请日：2011-02-10
申请人： Michael Fee , Christian Habermann , Christian Jacobi , Diana L. Orf , Martin Recktenwald , Hans-Werner Tast , Ralf Winkelmann
发明人： Michael Fee , Christian Habermann , Christian Jacobi , Diana L. Orf , Martin Recktenwald , Hans-Werner Tast , Ralf Winkelmann
IPC分类号： H03M13/00
CPC分类号： G06F11/1064
摘要： Handling corrupted background data in an out of order processing environment. Modified data is stored on a byte of a word having at least one byte of background data. A byte valid vector and a byte store bit are added to the word. Parity checking is done on the word. If the word does not contain corrupted background date, the word is propagated to the next level of cache. If the word contains corrupted background data, a copy of the word is fetched from a next level of cache that is ECC protected, the byte having the modified data is extracted from the word and swapped for the corresponding byte in the word copy. The word copy is then written into the next level of cache that is ECC protected.
摘要翻译： 在乱序处理环境中处理损坏的背景数据。 修改的数据存储在具有至少一个字节的背景数据的字的字节上。 一个字节有效向量和一个字节存储位被加到该字中。 对这个词进行奇偶校验。 如果该单词不包含损坏的背景日期，该单词将传播到下一级缓存。 如果该单词包含已损坏的背景数据，则该字的副本将从ECC保护的高级缓存中提取，具有修改后的数据的字节将从该字中提取出来并交换为字副本中的相应字节。 然后将该字复制到被保护的ECC缓存的下一级。
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公开(公告)号：US08516200B2
公开(公告)日：2013-08-20
申请号：US12876366
申请日：2010-09-07
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F12/0811
摘要： A mechanism is provided for avoiding cross-interrogates for a streaming data optimized level one cache. The mechanism adds a set of dedicated registers, referred to as “copex registers,” to track ownership of the cache lines that the co-processor's L1 cache holds exclusive. The mechanism extends the cache directory of the L2 cache by a bit that identifies exclusive ownership of a cache line in the co-processor cache. The co-processor continuously provides an indication of which copex registers are valid. On any action that requires a directory lookup in the L2 cache, the mechanism compares the valid copex registers against the lookup address in parallel to the directory lookup. The mechanism considers the “exclusive ownership in co-processor” bit in the directory valid only if the cache line is also currently in a valid copex register.
摘要翻译： 提供了一种用于避免流数据优化的一级缓存的交叉询问的机制。 该机制添加了一组专用寄存器（称为“copex寄存器”）来跟踪协处理器的L1高速缓存保存的高速缓存行的所有权。 该机制将L2高速缓存的缓存目录扩展一个位，以识别协处理器高速缓存中高速缓存行的独占所有权。 协处理器连续提供哪些共享寄存器有效的指示。 对于需要在L2缓存中进行目录查找的任何操作，该机制将将有效的copex寄存器与查找地址并行地与目录查找进行比较。 该机制认为目录中的“独占所有权协同处理器”位只有当高速缓存行当前还在有效的copex寄存器中时才有效。
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4.发明申请公开(公告)号：US20120210188A1
公开(公告)日：2012-08-16
申请号：US13024775
申请日：2011-02-10
申请人： Michael Fee , Christian Habermann , Christian Jacobi , Diana L. Orf , Martin Recktenwald , Hans-Werner Tast , Ralf Winkelmann
发明人： Michael Fee , Christian Habermann , Christian Jacobi , Diana L. Orf , Martin Recktenwald , Hans-Werner Tast , Ralf Winkelmann
IPC分类号： G06F11/10
CPC分类号： G06F11/1064
摘要： Handling corrupted background data in an out of order processing environment. Modified data is stored on a byte of a word having at least one byte of background data. A byte valid vector and a byte store bit are added to the word. Parity checking is done on the word. If the word does not contain corrupted background date, the word is propagated to the next level of cache. If the word contains corrupted background data, a copy of the word is fetched from a next level of cache that is ECC protected, the byte having the modified data is extracted from the word and swapped for the corresponding byte in the word copy. The word copy is then written into the next level of cache that is ECC protected.
摘要翻译： 在乱序处理环境中处理损坏的背景数据。 修改的数据存储在具有至少一个字节的背景数据的字的字节上。 一个字节有效向量和一个字节存储位被加到该字中。 对这个词进行奇偶校验。 如果该单词不包含损坏的背景日期，该单词将传播到下一级缓存。 如果该单词包含已损坏的背景数据，则该字的副本将从ECC保护的高级缓存中提取，具有修改后的数据的字节将从该字中提取出来并交换为字副本中的相应字节。 然后将该字复制到被保护的ECC缓存的下一级。
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公开(公告)号：US20140082290A1
公开(公告)日：2014-03-20
申请号：US13621328
申请日：2012-09-17
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0844 , G06F12/0893 , G06F2212/1016 , G06F2212/6042
摘要： A mechanism is provided in a data processing system for enhancing wiring structure for a cache supporting an auxiliary data output. The mechanism splits the data cache into a first data portion and a second data portion. The first data portion provides a first set of data elements and the second data portion provides a second set of data elements. The mechanism connects a first data path to provide the first set of data elements to a primary output and connects a second data path to provide the second set of data elements to the primary output. The mechanism feeds the first data path back into the second data path and feeds the second data path back into the first data path. The mechanism connects a secondary output to the second data path.
摘要翻译： 在用于增强支持辅助数据输出的高速缓存的布线结构的数据处理系统中提供一种机制。 该机制将数据高速缓存分解成第一数据部分和第二数据部分。 第一数据部分提供第一组数据元素，第二数据部分提供第二组数据元素。 该机制连接第一数据路径以将第一组数据元素提供给主输出，并连接第二数据路径以将第二组数据元素提供给主输出。 该机构将第一数据路径馈送回第二数据路径并将第二数据路径馈送回第一数据路径。 该机制将辅助输出连接到第二数据路径。
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6.发明授权公开(公告)号：US08891279B2
公开(公告)日：2014-11-18
申请号：US13621328
申请日：2012-09-17
IPC分类号： G11C5/06
CPC分类号： G06F12/0897 , G06F12/0844 , G06F12/0893 , G06F2212/1016 , G06F2212/6042
摘要： A mechanism is provided in a data processing system for enhancing wiring structure for a cache supporting an auxiliary data output. The mechanism splits the data cache into a first data portion and a second data portion. The first data portion provides a first set of data elements and the second data portion provides a second set of data elements. The mechanism connects a first data path to provide the first set of data elements to a primary output and connects a second data path to provide the second set of data elements to the primary output. The mechanism feeds the first data path back into the second data path and feeds the second data path back into the first data path. The mechanism connects a secondary output to the second data path.
摘要翻译： 在用于增强支持辅助数据输出的高速缓存的布线结构的数据处理系统中提供一种机制。 该机制将数据高速缓存分解成第一数据部分和第二数据部分。 第一数据部分提供第一组数据元素，第二数据部分提供第二组数据元素。 该机制连接第一数据路径以将第一组数据元素提供给主输出，并连接第二数据路径以将第二组数据元素提供给主输出。 该机构将第一数据路径馈送回第二数据路径并将第二数据路径馈送回第一数据路径。 该机制将辅助输出连接到第二数据路径。
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公开(公告)号：US08751749B2
公开(公告)日：2014-06-10
申请号：US13159590
申请日：2011-06-14
摘要： Data caching for use in a computer system including a lower cache memory and a higher cache memory. The higher cache memory receives a fetch request. It is then determined by the higher cache memory the state of the entry to be replaced next. If the state of the entry to be replaced next indicates that the entry is exclusively owned or modified, the state of the entry to be replaced next is changed such that a following cache access is processed at a higher speed compared to an access processed if the state would stay unchanged.
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公开(公告)号：US20120215983A1
公开(公告)日：2012-08-23
申请号：US13459121
申请日：2012-04-28
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/12 , G06F2212/507
摘要： Data caching for use in a computer system including a lower cache memory and a higher cache memory. The higher cache memory receives a fetch request. It is then determined by the higher cache memory the state of the entry to be replaced next. If the state of the entry to be replaced next indicates that the entry is exclusively owned or modified, the state of the entry to be replaced next is changed such that a following cache access is processed at a higher speed compared to an access processed if the state would stay unchanged.
摘要翻译： 数据缓存用于包括较低级高速缓冲存储器和较高级缓存的计算机系统。 较高的缓存存储器接收提取请求。 然后由更高的缓存存储器确定要被替换的条目的状态。 如果接下来被替换的条目的状态指示该条目是专门拥有或修改的，则下一个被替换的条目的状态被改变，使得如果处理的访问与处理的访问相比，以更高的速度处理以下高速缓存访问 国家将保持不变。
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公开(公告)号：US09075732B2
公开(公告)日：2015-07-07
申请号：US13159590
申请日：2011-06-14
CPC分类号： G06F12/0897 , G06F12/12 , G06F2212/507
摘要： Data caching for use in a computer system including a lower cache memory and a higher cache memory. The higher cache memory receives a fetch request. It is then determined by the higher cache memory the state of the entry to be replaced next. If the state of the entry to be replaced next indicates that the entry is exclusively owned or modified, the state of the entry to be replaced next is changed such that a following cache access is processed at a higher speed compared to an access processed if the state would stay unchanged.
摘要翻译： 数据缓存用于包括较低级高速缓冲存储器和较高级缓存的计算机系统。 较高的缓存存储器接收提取请求。 然后由更高的缓存存储器确定要被替换的条目的状态。 如果接下来被替换的条目的状态指示该条目是专门拥有或修改的，则下一个被替换的条目的状态被改变，使得如果处理的访问与处理的访问相比，以更高的速度处理以下高速缓存访问 国家将保持不变。
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公开(公告)号：US08856444B2
公开(公告)日：2014-10-07
申请号：US13459121
申请日：2012-04-28
CPC分类号： G06F12/0897 , G06F12/12 , G06F2212/507
摘要： Data caching for use in a computer system including a lower cache memory and a higher cache memory. The higher cache memory receives a fetch request. It is then determined by the higher cache memory the state of the entry to be replaced next. If the state of the entry to be replaced next indicates that the entry is exclusively owned or modified, the state of the entry to be replaced next is changed such that a following cache access is processed at a higher speed compared to an access processed if the state would stay unchanged.
摘要翻译： 数据缓存用于包括较低级高速缓冲存储器和较高级缓存的计算机系统。 较高的缓存存储器接收提取请求。 然后由更高的缓存存储器确定要被替换的条目的状态。 如果接下来被替换的条目的状态指示该条目是专门拥有或修改的，则下一个被替换的条目的状态被改变，使得如果处理的访问与处理的访问相比，以更高的速度处理以下高速缓存访问 国家将保持不变。
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