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公开(公告)号：US07323388B2
公开(公告)日：2008-01-29
申请号：US11072695
申请日：2005-03-04
IPC分类号： H01L29/417
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A trench (2) is fabricated in a silicon body (1). The walls (4) of the trench are provided with a nitrogen implantation (6). An oxide layer between the source/drain regions (5) and a word line applied on the top side grows to a greater thickness than a lower oxide layer of an ONO storage layer fabricated as gate dielectric at the trench wall. Instead of the nitrogen implantation into the trench walls, it is possible to fabricate a metal silicide layer on the top sides of the source/drain regions in order to accelerate the oxide growth there.
摘要翻译： 在硅体（1）中制造沟槽（2）。 沟槽的壁（4）设置有氮注入（6）。 源极/漏极区域（5）和施加在顶侧的字线之间的氧化物层比在沟槽壁上制作为栅极电介质的ONO存储层的低氧化物层增长更大的厚度。 代替氮注入到沟槽壁中，可以在源极/漏极区的顶侧上制造金属硅化物层，以加速其中的氧化物生长。
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公开(公告)号：US07094648B2
公开(公告)日：2006-08-22
申请号：US11023041
申请日：2004-12-27
IPC分类号： H01L21/8236
CPC分类号： H01L21/28282 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L27/11573 , H01L29/66833
摘要： In the method, trenches are etched and, in between, bit lines (8) are in each case arranged on doped source/drain regions (3, 4). Storage layers (5, 6, 7) are applied and gate electrodes (2) are arranged at the trench walls. After the introduction of polysilicon, which is provided for the gate electrodes (2), into the trenches, the top side is ground back in a planarizing manner until the top side of the covering layer (16) is reached, and afterward a polysilicon layer (18), which is provided for the word lines, is applied over the whole area and patterned to form the word lines.
摘要翻译： 在该方法中，蚀刻沟槽，并且在其间，位线（8）分别布置在掺杂的源极/漏极区域（3,4）上。 存储层（5,6,7）被施加，栅电极（2）布置在沟槽壁处。 在向栅极电极（2）引入向多个沟槽中引入的多晶硅之后，以平坦化的方式将顶面进行研磨，直到到达覆盖层（16）的顶侧，然后将多晶硅层 （18），其被设置用于字线，并且被图案化以形成字线。
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公开(公告)号：US20050164456A1
公开(公告)日：2005-07-28
申请号：US11023041
申请日：2004-12-27
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/302 , H01L21/336 , H01L21/8234 , H01L21/8246 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28282 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L27/11573 , H01L29/66833
摘要： In the method, trenches are etched and, in between, bit lines (8) are in each case arranged on doped source/drain regions (3, 4). Storage layers (5, 6, 7) are applied and gate electrodes (2) are arranged at the trench walls. After the introduction of polysilicon, which is provided for the gate electrodes (2), into the trenches, the top side is ground back in a planarizing manner until the top side of the covering layer (16) is reached, and afterward a polysilicon layer (18), which is provided for the word lines, is applied over the whole area and patterned to form the word lines.
摘要翻译： 在该方法中，蚀刻沟槽，并且在其间，位线（8）分别布置在掺杂的源极/漏极区域（3,4）上。 存储层（5,6,7）被施加，栅电极（2）布置在沟槽壁处。 在向栅极电极（2）引入向多个沟槽中引入的多晶硅之后，以平坦化的方式将顶面进行研磨，直到到达覆盖层（16）的顶侧，然后将多晶硅层 （18），其被设置用于字线，并且被图案化以形成字线。
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公开(公告)号：US20050085037A1
公开(公告)日：2005-04-21
申请号：US11006049
申请日：2004-12-07
IPC分类号： H01L29/41 , H01L21/8242 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L27/115
摘要： An electrically conductive bit line layer is applied and patterned into portions arranged parallel to one another before the trench is etched into the semiconductor material, in which case, after the patterning of the bit line layer (3, 4) and before the etching of the trench, an implantation is introduced for the purpose of defining the position of the junctions, or, after the implantation of the n+-type well (19) for the source/drain regions, the bit line layer (3, 4) is patterned using an etching stop layer (2) arranged on the semiconductor body (1).
摘要翻译： 在沟槽被蚀刻到半导体材料之前，将导电位线层施加并图案化成彼此平行布置的部分，在这种情况下，在位线层（3,4）的图案化之后并且在蚀刻 引入注入用于限定结的位置，或者在用于源极/漏极区的n + H +型阱（19）的注入之后，位线层 （3,4）使用布置在半导体本体（1）上的蚀刻停止层（2）进行图案化。
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公开(公告)号：US07205195B2
公开(公告)日：2007-04-17
申请号：US11006049
申请日：2004-12-07
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： An electrically conductive bit line layer is applied and patterned into portions arranged parallel to one another before the trench is etched into the semiconductor material, in which case, after the patterning of the bit line layer (3, 4) and before the etching of the trench, an implantation is introduced for the purpose of defining the position of the junctions, or, after the implantation of the n+-type well (19) for the source/drain regions, the bit line layer (3, 4) is patterned using an etching stop layer (2) arranged on the semiconductor body (1).
摘要翻译： 在沟槽被蚀刻到半导体材料之前，将导电位线层施加并图案化成彼此平行布置的部分，在这种情况下，在位线层（3,4）的图案化之后并且在蚀刻 引入注入用于限定结的位置，或者在用于源极/漏极区的n + H +型阱（19）的注入之后，位线层 （3,4）使用布置在半导体本体（1）上的蚀刻停止层（2）进行图案化。
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公开(公告)号：US20050196923A1
公开(公告)日：2005-09-08
申请号：US11072695
申请日：2005-03-04
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8246 , H01L27/115 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A trench (2) is fabricated in a silicon body (1). The walls (4) of the trench are provided with a nitrogen implantation (6). An oxide layer between the source/drain regions (5) and a word line applied on the top side grows to a greater thickness than a lower oxide layer of an ONO storage layer fabricated as gate dielectric at the trench wall. Instead of the nitrogen implantation into the trench walls, it is possible to fabricate a metal silicide layer on the top sides of the source/drain regions in order to accelerate the oxide growth there.
摘要翻译： 在硅体（1）中制造沟槽（2）。 沟槽的壁（4）设置有氮注入（6）。 源极/漏极区域（5）和施加在顶侧的字线之间的氧化物层比在沟槽壁上制作为栅极电介质的ONO存储层的低氧化物层增长更大的厚度。 代替氮注入到沟槽壁中，可以在源极/漏极区的顶侧上制造金属硅化物层，以加速其中的氧化物生长。
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7.发明授权Method for fabricating semiconductor memories with charge trapping memory cells 失效用电荷俘获存储单元制造半导体存储器的方法公开(公告)号：US07005355B2
公开(公告)日：2006-02-28
申请号：US10735411
申请日：2003-12-12
IPC分类号： H01L21/74 , H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for manufacturing a semiconductor device includes forming a storage layer over a semiconductor body. The storage layer includes a first boundary layer, an intermediate storage layer and a second boundary layer. The storage layer is patterned so that at least some of the storage layer is removed from over a first portion of the semiconductor body and some of the storage layer is removed from over a second portion of the semiconductor body. The first portion of the semiconductor body is doped and the second portion of the semiconductor body is etched.
摘要翻译： 一种制造半导体器件的方法包括：在半导体本体上形成存储层。 存储层包括第一边界层，中间存储层和第二边界层。 存储层被图案化，使得存储层中的至少一些从半导体主体的第一部分上方移除，并且存储层中的一些从半导体本体的第二部分上移除。 半导体本体的第一部分被掺杂，半导体本体的第二部分被蚀刻。
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公开(公告)号：US07274069B2
公开(公告)日：2007-09-25
申请号：US10913707
申请日：2004-08-05
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/792 , H01L21/28282
摘要： In a memory cell, in a trench, a layer sequence comprising a first oxide layer, a nitride layer provided on the first oxide layer, and a second oxide layer, facing the gate electrode, and provided at the lateral trench walls, while the nitride layer is absent in a curved region of the trench bottom. In an alternative configuration, in each case at least one step is formed at the lateral walls of the trench, preferably below the source region or the drain region, respectively.
摘要翻译： 在存储器单元中，在沟槽中，包括第一氧化物层，设置在第一氧化物层上的氮化物层和面向栅电极的第二氧化物层并且设置在侧向沟槽壁处的层序列，而氮化物 在沟槽底部的弯曲区域中不存在层。 在替代配置中，在每种情况下，在沟槽的侧壁上分别形成至少一个台阶，优选地分别在源区域或漏极区域下方形成。
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9.发明授权Method for fabricating a semiconductor memory having charge trapping memory cells and semiconductor substrate 失效一种制造具有电荷捕获存储单元和半导体衬底的半导体存储器的方法公开(公告)号：US07015095B2
公开(公告)日：2006-03-21
申请号：US10856414
申请日：2004-05-27
申请人： Mathias Krause , Christoph Ludwig , Jens-Uwe Sachse , Joachim Deppe , Ralf Richter , Christoph Kleint , Ricardo Mikalo
发明人： Mathias Krause , Christoph Ludwig , Jens-Uwe Sachse , Joachim Deppe , Ralf Richter , Christoph Kleint , Ricardo Mikalo
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： Electrically conductive material is introduced into interspaces between the word lines (2) and is partially removed using a mask (6) in such a way that residual portions (7) of the conductive material in each case fill a section of the relevant interspace and produce an electrical contact with source/drain regions (15). With further portions of the conductive material, it is possible to form alignment marks for the fabrication process.
摘要翻译： 导电材料被引入到字线（2）之间的间隙中，并且使用掩模（6）部分地移除，使得导电材料的残留部分（7）在每种情况下填充相关间隙的一部分并产生 与源/漏区（15）的电接触。 对于导电材料的另外部分，可以形成用于制造工艺的对准标记。
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公开(公告)号：US07323383B2
公开(公告)日：2008-01-29
申请号：US11015747
申请日：2004-12-17
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L2924/0002 , H01L2924/00
摘要： In the method, trenches (9) are etched and, in between, bit lines (8) are in each case arranged on doped source drain/regions (3). Dopant is introduced into the bottoms of the trenches (9) in order to form doped regions (23), in order to electrically modify the channel regions. Storage layers are applied and gate electrodes (2) are arranged at the trench walls. The semiconductor material at the bottoms of the trenches is etched away between the word lines (18/19) to an extent such that the doped regions (23) are removed there to such a large extent that a crosstalk between adjacent memory cells along the trenches is reduced.
摘要翻译： 在该方法中，蚀刻沟槽（9），并且在其间，位线（8）分别布置在掺杂源极漏极/区域（3）上。 掺杂剂被引入沟槽（9）的底部以便形成掺杂区域（23），以便电修改沟道区域。 存储层被施加，栅电极（2）布置在沟槽壁处。 在沟槽底部的半导体材料在字线（18/19）之间被蚀刻掉到一定程度上，使得掺杂区域（23）在那里被移除到如此大的程度，使得沿着沟槽的相邻存储器单元之间的串扰 降低了。
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