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公开(公告)号：US06433436B1
公开(公告)日：2002-08-13
申请号：US09320612
申请日：1999-05-26
IPC分类号： H01L2348
CPC分类号： H01L23/5226 , H01L21/7682 , H01L21/76885 , H01L21/76897 , H01L23/53223 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A structure and process to define a via/interconnect structure is described. The structure is formed by reactive ion etching (RIE) where vias are formed first then the interconnects. The disclosed method relies on first depositing a metal with a thickness equivalent to the total height of the via and interconnect. Once vias are delineated by forming a hard mask and lithography, the lines are patterned using a lithographic step. Vias and lines are formed using lithography and RIE in one step and interfacial integrity is maintained resulting in high electromigration performance.
摘要翻译： 描述了定义通孔/互连结构的结构和过程。 该结构由反应离子蚀刻（RIE）形成，其中首先形成通孔和互连。 所公开的方法依赖于首先沉积具有等于通孔和互连的总高度的厚度的金属。 一旦通过形成硬掩模和光刻来描绘通孔，则使用光刻步骤对线进行图案化。 通过光刻和RIE在一个步骤中形成通孔和线，并保持界面完整性，导致高的电迁移性能。
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公开(公告)号：US06444565B1
公开(公告)日：2002-09-03
申请号：US09896204
申请日：2001-06-29
IPC分类号： H01L214761
CPC分类号： H01L23/5226 , H01L21/7682 , H01L21/76885 , H01L21/76897 , H01L23/53223 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A structure and process to define a via/interconnect structure is described. The structure is formed by reactive ion etching (RIE) where vias are formed first then the interconnects. The disclosed method relies on first depositing a metal with a thickness equivalent to the total height of the via and interconnect. Once vias are delineated by forming a hard mask and lithography, the lines are patterned using a lithographic step. Vias and lines are formed using lithography and RIE in one step and interfacial integrity is maintained resulting in high electromigration performance.
摘要翻译： 描述了定义通孔/互连结构的结构和过程。 该结构由反应离子蚀刻（RIE）形成，其中首先形成通孔和互连。 所公开的方法依赖于首先沉积具有等于通孔和互连的总高度的厚度的金属。 一旦通过形成硬掩模和光刻来描绘通孔，则使用光刻步骤对线进行图案化。 通过光刻和RIE在一个步骤中形成通孔和线，并保持界面完整性，导致高的电迁移性能。
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3.发明授权公开(公告)号：US07119545B2
公开(公告)日：2006-10-10
申请号：US10711641
申请日：2004-09-29
申请人： Ishtiaq Ahsan , Ronald Gene Filippi , Roy Charles Iggulden , Edward William Kiewra , Ping-Chuan Wang
发明人： Ishtiaq Ahsan , Ronald Gene Filippi , Roy Charles Iggulden , Edward William Kiewra , Ping-Chuan Wang
CPC分类号： H01L22/34 , G01R31/2858 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for detecting metal extrusion associated with electromigration (EM) under high current density situations within an EM test line by measuring changes in capacitance associated with metal extrusion that occurs in the vicinity of the charge carrying surfaces of one or more capacitors situated in locations of close physical proximity to anticipated sites of metal extrusion on an EM test line are provided. The capacitance of each of the one or more capacitors is measured prior to and then during or after operation of the EM test line so as to detect capacitance changes indicating metal extrusion.
摘要翻译： 一种用于在EM测试线中的高电流密度情况下检测与电迁移（EM）有关的金属挤出的方法和装置，其通过测量在位于一个或多个电容器中的一个或多个电容器的电荷承载表面附近的与金属挤出相关的电容的变化 提供了在EM测试线上与金属挤压的预期位置紧密物理接近的位置。 一个或多个电容器中的每一个的电容在EM测试线之前和之后测量，以便检测指示金属挤压的电容变化。
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公开(公告)号：US20130153964A1
公开(公告)日：2013-06-20
申请号：US13326825
申请日：2011-12-15
申请人： Dechao Guo , Shu-Jen Han , Edward William Kiewra , Kuen-Ting Shiu
发明人： Dechao Guo , Shu-Jen Han , Edward William Kiewra , Kuen-Ting Shiu
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/8258 , H01L21/823807 , H01L27/0605
摘要： Techniques for employing different channel materials within the same CMOS circuit are provided. In one aspect, a method of fabricating a CMOS circuit includes the following steps. A wafer is provided having a first semiconductor layer on an insulator. STI is used to divide the first semiconductor layer into a first active region and a second active region. The first semiconductor layer is recessed in the first active region. A second semiconductor layer is epitaxially grown on the first semiconductor layer, wherein the second semiconductor layer comprises a material having at least one group III element and at least one group V element. An n-FET is formed in the first active region using the second semiconductor layer as a channel material for the n-FET. A p-FET is formed in the second active region using the first semiconductor layer as a channel material for the p-FET.
摘要翻译： 提供在同一CMOS电路内采用不同通道材料的技术。 一方面，制造CMOS电路的方法包括以下步骤。 提供了在绝缘体上具有第一半导体层的晶片。 STI用于将第一半导体层分成第一有源区和第二有源区。 第一半导体层凹入第一有源区。 第二半导体层在第一半导体层上外延生长，其中第二半导体层包括具有至少一个III族元素和至少一个V族元素的材料。 使用第二半导体层作为n-FET的沟道材料，在第一有源区中形成n-FET。 使用第一半导体层作为p-FET的沟道材料，在第二有源区中形成p-FET。
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公开(公告)号：US5670018A
公开(公告)日：1997-09-23
申请号：US430011
申请日：1995-04-27
申请人： Elke Eckstein , Birgit Hoffman, deceased , Edward William Kiewra , Waldemar Walter Kocon , Marc Jay Weiss
发明人： Elke Eckstein , Birgit Hoffman, deceased , Edward William Kiewra , Waldemar Walter Kocon , Marc Jay Weiss
IPC分类号： C23F4/00 , H01L21/302 , H01L21/3065 , H01L21/3213 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/32137 , Y10S438/963
摘要： A back end of the line dry etch method is disclosed. Etching of a mask oxide and temporary (sacrificial) silicon mandrel occurs following the formation of gate stacks and tungsten studs. The mask oxide is etched selectively to tungsten and silicon through the use of a polymerizing oxide etch. The silicon is etched selectively to both silicon nitride, silicon oxide, and tungsten. The process removes the silicon mandrel and associated silicon residual stringers by removing backside helium cooling, while using HBr as the single species etchant, and by adjusting the duration, the pressure, and the electrode gaps during the silicon etch process. The silicon may be undoped polysilicon, doped polysilicon, or single crystal silicon.
摘要翻译： 公开了线干法蚀刻方法的后端。 掩模氧化物和临时（牺牲）硅心轴的蚀刻在栅堆叠和钨钉形成之后发生。 通过使用聚合氧化物蚀刻，对钨和硅选择性地蚀刻掩模氧化物。 硅被选择性地蚀刻到氮化硅，氧化硅和钨两者。 该方法通过去除背面的氦冷却，同时使用HBr作为单一种类蚀刻剂，并通过在硅蚀刻工艺期间调节持续时间，压力和电极间隙来移除硅心轴和相关硅残余桁条。 硅可以是未掺杂的多晶硅，掺杂多晶硅或单晶硅。
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公开(公告)号：US08610172B2
公开(公告)日：2013-12-17
申请号：US13326825
申请日：2011-12-15
申请人： Dechao Guo , Shu-Jen Han , Edward William Kiewra , Kuen-Ting Shiu
发明人： Dechao Guo , Shu-Jen Han , Edward William Kiewra , Kuen-Ting Shiu
IPC分类号： H01L29/66
CPC分类号： H01L21/8258 , H01L21/823807 , H01L27/0605
摘要： Techniques for employing different channel materials within the same CMOS circuit are provided. In one aspect, a method of fabricating a CMOS circuit includes the following steps. A wafer is provided having a first semiconductor layer on an insulator. STI is used to divide the first semiconductor layer into a first active region and a second active region. The first semiconductor layer is recessed in the first active region. A second semiconductor layer is epitaxially grown on the first semiconductor layer, wherein the second semiconductor layer comprises a material having at least one group III element and at least one group V element. An n-FET is formed in the first active region using the second semiconductor layer as a channel material for the n-FET. A p-FET is formed in the second active region using the first semiconductor layer as a channel material for the p-FET.
摘要翻译： 提供在同一CMOS电路内采用不同通道材料的技术。 一方面，制造CMOS电路的方法包括以下步骤。 提供了在绝缘体上具有第一半导体层的晶片。 STI用于将第一半导体层分成第一有源区和第二有源区。 第一半导体层凹入第一有源区。 第二半导体层在第一半导体层上外延生长，其中第二半导体层包括具有至少一个III族元素和至少一个V族元素的材料。 使用第二半导体层作为n-FET的沟道材料，在第一有源区中形成n-FET。 使用第一半导体层作为p-FET的沟道材料，在第二有源区中形成p-FET。
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