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1.发明授权Trench structure having one or more diodes embedded therein adjacent a PN junction 有权沟槽结构，其中一个或多个二极管嵌入其中，邻近PN结公开(公告)号：US07132712B2
公开(公告)日：2006-11-07
申请号：US10288982
申请日：2002-11-05
IPC分类号： H01L29/72
CPC分类号： H01L29/7816 , H01L29/0653 , H01L29/404 , H01L29/407 , H01L29/7802 , H01L29/7813 , H01L29/7818 , H01L29/861
摘要： In accordance with an embodiment of the invention, a semiconductor structure includes a semiconductor region having a P-type region and a N-type region forming a PN junction therebetween. A first trench extends in the semiconductor region adjacent at least one of the P-type and N-type regions. The first trench includes at least one diode therein.
摘要翻译： 根据本发明的实施例，半导体结构包括具有P型区域和在其间形成PN结的N型区域的半导体区域。 第一沟槽在邻近P型和N型区域中的至少一个的半导体区域中延伸。 第一沟槽在其中包括至少一个二极管。
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2.发明授权Method of forming a trench structure having one or more diodes embedded therein adjacent a PN junction 有权形成具有嵌入其中的一个或多个二极管的沟槽结构邻近PN结的方法公开(公告)号：US07582519B2
公开(公告)日：2009-09-01
申请号：US11487015
申请日：2006-07-14
IPC分类号： H01L29/72
CPC分类号： H01L29/7816 , H01L29/0653 , H01L29/404 , H01L29/407 , H01L29/7802 , H01L29/7813 , H01L29/7818 , H01L29/861
摘要： A semiconductor structure is formed as follows. A semiconductor region is formed to have a P-type region and a N-type region forming a PN junction therebetween. A first trench is formed extending in the semiconductor region adjacent at least one of the P-type and N-type regions is formed. At least one diode is formed in the trench.
摘要翻译： 如下形成半导体结构。 半导体区域形成为具有P型区域和在其间形成PN结的N型区域。 形成在邻近的P型和N型区域中的至少一个的半导体区域中延伸的第一沟槽。 在沟槽中形成至少一个二极管。
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公开(公告)号：US20130087852A1
公开(公告)日：2013-04-11
申请号：US13267712
申请日：2011-10-06
申请人： Suku Kim , Joseph Andrew Yedinak , Ihsiu Ho
发明人： Suku Kim , Joseph Andrew Yedinak , Ihsiu Ho
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/1095 , H01L29/4236 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/66734 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： Edge termination structures for power semiconductor devices and methods for making such structures are described. The power semiconductor devices (or power devices) contain a substrate with an epitaxial layer thereon, an array of substantially-parallel, active trenches formed in the epitaxial layer, with the active trenches containing a transistor structure with an insulated gate conducting layer, a superjunction or shielded region adjacent the active trenches; a peripheral trench surrounding the active trenches, and a source contact area within an upper surface of the epitaxial layer, where the gate conducting layer extends over the superjunction or shielded region and over the surrounding peripheral trench. Such a configuration allows the edge termination structure to be used with a wide range of breakdown voltages in power MOSFET devices containing PN superjunction structures. Other embodiments are described.
摘要翻译： 描述用于功率半导体器件的边缘终端结构及其制造方法。 功率半导体器件（或功率器件）包含其上具有外延层的衬底，形成在外延层中的基本上平行的有源沟槽的阵列，其中有源沟槽包含具有绝缘栅极导电层的晶体管结构，超级结 或与有源沟槽相邻的屏蔽区域; 围绕有源沟槽的外围沟槽，以及在外延层的上表面内的源极接触区域，其中栅极导电层在超结或屏蔽区域上延伸并在周围的周边沟槽上方延伸。 这种配置允许边缘终端结构在包含PN超结构结构的功率MOSFET器件中与宽范围的击穿电压一起使用。 描述其他实施例。
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4.发明授权Method of forming power semiconductor devices with controllable integrated buffer 失效用可控集成缓冲器形成功率半导体器件的方法
公开(公告)号：US5872028A
公开(公告)日：1999-02-16
申请号：US708712
申请日：1996-09-05
IPC分类号： H01L29/78 , H01L21/22 , H01L21/331 , H01L21/336 , H01L29/739 , H01L21/332
CPC分类号： H01L29/66333 , H01L21/2205 , H01L29/7395
摘要： A method of manufacturing a semiconductor device and device in which a sacrificial N shelf layer is grown on a P+ semiconductor substrate to contain the out-diffusion of dopant from the substrate. An N+ buffer layer is grown on the N shelf layer and an N- epitaxial layer is grown on the N+ buffer layer. The presence of the N shelf layer, which is consumed by the substrate dopant during further device fabrication, allows the integrated dopant level of the N+ buffer layer to be accurately controlled in the finished device.
摘要翻译： 一种半导体器件和器件的制造方法，其中在P +半导体衬底上生长牺牲N搁架层以包含来自衬底的掺杂剂的扩散。 在N层上生长N +缓冲层，在N +缓冲层上生长N外延层。 在进一步的器件制造期间由衬底掺杂剂消耗的N层层的存在允许在最终器件中精确地控制N +缓冲层的集成掺杂剂水平。
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