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    Determination of wake signal initiation on shared wake pins in computing devices
    2.
    发明授权
    Determination of wake signal initiation on shared wake pins in computing devices 有权
    确定计算设备中共享唤醒引脚上的唤醒信号启动

    公开(公告)号：US09032225B2

    公开(公告)日：2015-05-12

    申请号：US13523812

    申请日：2012-06-14

    申请人： Christopher J. Lake ,  Bhushan Vaidya ,  William Knolla ,  Michael N. Derr ,  Yitschak Kapschitz ,  Reuven Rozic

    发明人： Christopher J. Lake ,  Bhushan Vaidya ,  William Knolla ,  Michael N. Derr ,  Yitschak Kapschitz ,  Reuven Rozic

    IPC分类号： G06F1/26

    CPC分类号： G06F1/26 ,  G06F1/22 ,  G06F1/3206 ,  G06F2213/2422

    摘要： Embodiments of computer-implemented methods, systems, computing devices, and computer-readable media are described herein for transitioning a computing device between a first state in which the computing device uses a first amount of power and a second state in which the computing device uses a second, greater amount of power. The computing device may include a shared wake pin to which a first external device and a second external device may be operably coupled, and a communication bus to which the first external device is connected and the second external device is not. Responsive to receipt of a wake signal at the wake pin, the computing device may transition between states, send an instruction to the first external device over the communication bus, and determine whether the first or second external device initiated the wake signal based on a response at the wake pin.

    摘要翻译： 本文描述了计算机实现的方法，系统，计算设备和计算机可读介质的实施例，用于在计算设备使用第一功率量的第一状态和计算设备使用的第二状态之间转换计算设备 一秒钟，更大的力量。 计算设备可以包括共享的唤醒引脚，第一外部设备和第二外部设备可以可操作地耦合到该共享的唤醒引脚，以及连接第一外部设备并且第二外部设备不连接的通信总线。 响应于在唤醒引脚处接收到唤醒信号，计算设备可以在状态之间转换，通过通信总线向第一外部设备发送指令，并且基于响应来确定第一或第二外部设备是否启动了唤醒信号 在尾针。

    UTILIZATION OF SHARED WAKE PINS IN COMPUTING DEVICES
    4.
    发明申请
    UTILIZATION OF SHARED WAKE PINS IN COMPUTING DEVICES 有权
    计算设备中共享的波形引脚的使用

    公开(公告)号：US20130339758A1

    公开(公告)日：2013-12-19

    申请号：US13523812

    申请日：2012-06-14

    申请人： Christopher J. Lake ,  Bhushan Vaidya ,  William Knolla ,  Michael N. Derr ,  Yitschak Kapschitz ,  Reuven Rozic

    发明人： Christopher J. Lake ,  Bhushan Vaidya ,  William Knolla ,  Michael N. Derr ,  Yitschak Kapschitz ,  Reuven Rozic

    IPC分类号： G06F1/26

    CPC分类号： G06F1/26 ,  G06F1/22 ,  G06F1/3206 ,  G06F2213/2422

    摘要： Embodiments of computer-implemented methods, systems, computing devices, and computer-readable media are described herein for transitioning a computing device between a first state in which the computing device uses a first amount of power and a second state in which the computing device uses a second, greater amount of power. The computing device may include a shared wake pin to which a first external device and a second external device may be operably coupled, and a communication bus to which the first external device is connected and the second external device is not. Responsive to receipt of a wake signal at the wake pin, the computing device may transition between states, send an instruction to the first external device over the communication bus, and determine whether the first or second external device initiated the wake signal based on a response at the wake pin.

    摘要翻译： 本文描述了计算机实现的方法，系统，计算设备和计算机可读介质的实施例，用于在其中计算设备使用第一功率量的第一状态和计算设备使用的第二状态之间转换计算设备 一秒钟，更大的力量。 计算设备可以包括共享的唤醒引脚，第一外部设备和第二外部设备可以可操作地耦合到该共享的唤醒引脚，以及连接第一外部设备并且第二外部设备不连接的通信总线。 响应于在唤醒引脚处接收到唤醒信号，计算设备可以在状态之间转换，通过通信总线向第一外部设备发送指令，并且基于响应来确定第一或第二外部设备是否启动了唤醒信号 在尾针。

    SYSTEM, METHOD, AND APPARATUS FOR DVSEC FOR EFFICIENT PERIPHERAL MANAGEMENT
    5.
    发明申请
    SYSTEM, METHOD, AND APPARATUS FOR DVSEC FOR EFFICIENT PERIPHERAL MANAGEMENT 审中-公开

    公开(公告)号：US20190042281A1

    公开(公告)日：2019-02-07

    申请号：US15987863

    申请日：2018-05-23

    申请人： Vinay Raghav ,  Reuven Rozic ,  David J. Harriman

    发明人： Vinay Raghav ,  Reuven Rozic ,  David J. Harriman

    IPC分类号： G06F9/445 ,  G06F13/10 ,  G06F13/42

    摘要： Aspects of the embodiments include systems, methods, devices, and computer program products to receive, from the downstream component, an indication of an extended capability; determining, from the indication, one or more configuration parameters for the downstream component; applying the one or more configuration parameters; and performing data signal or control signal transmissions across the PCIe-compliant link with the downstream component based, at least in part, on the applied one or more configuration parameters. The extended capabilities can be indicated by a DVSEC extended capability definition received from a downstream device. The extended capabilities of the downstream component can indicate the number of buses, the port type, the expandability capability, the D3Cold support status, the host router indicator, and/or the safe eject requirements of the downstream component.

    Circuitry to generate and/or use at least one transmission time in at least one descriptor
    6.
    发明授权
    Circuitry to generate and/or use at least one transmission time in at least one descriptor 有权
    在至少一个描述符中生成和/或使用至少一个传输时间的电路

    公开(公告)号：US09405719B2

    公开(公告)日：2016-08-02

    申请号：US13993710

    申请日：2011-11-11

    申请人： Reuven Rozic ,  Eric K. Mann

    发明人： Reuven Rozic ,  Eric K. Mann

    IPC分类号： G06F13/42 ,  H04L12/815 ,  H04L12/875 ,  H04L12/801

    CPC分类号： G06F13/42 ,  H04L47/12 ,  H04L47/22 ,  H04L47/564 ,  Y02D10/14 ,  Y02D10/151

    摘要： An embodiment may include circuitry that may generate and/or use, at least in part, at least one descriptor to be associated with at least one packet. The at least one descriptor may specify at least one transmission time at which the at least one packet is to be transmitted. The at least one transmission time may be specified in the at least one descriptor in such a manner as to permit the at least one transmission time to be explicitly identified based at least in part upon the at least one descriptor. Many alternatives, modifications, and variations are possible without departing from this embodiment.

    摘要翻译： 实施例可以包括可以至少部分地生成和/或使用与至少一个分组相关联的至少一个描述符的电路。 所述至少一个描述符可以指定至少一个发送所述至少一个分组的传输时间。 至少一个发送时间可以以至少部分地基于至少一个描述符来明确地识别至少一个发送时间的方式在至少一个描述符中被指定。 在不脱离本实施例的情况下，可以进行许多替换，修改和变化。

    CIRCUITRY TO GENERATE AND/OR USE AT LEAST ONE TRANSMISSION TIME IN AT LEAST ONE DESCRIPTOR
    7.
    发明申请
    CIRCUITRY TO GENERATE AND/OR USE AT LEAST ONE TRANSMISSION TIME IN AT LEAST ONE DESCRIPTOR 有权
    在至少一个描述符下生成和/或使用至少一个传输时间

    公开(公告)号：US20130304953A1

    公开(公告)日：2013-11-14

    申请号：US13993710

    申请日：2011-11-11

    申请人： Reuven Rozic ,  Eric K. Mann

    发明人： Reuven Rozic ,  Eric K. Mann

    IPC分类号： G06F13/42

    CPC分类号： G06F13/42 ,  H04L47/12 ,  H04L47/22 ,  H04L47/564 ,  Y02D10/14 ,  Y02D10/151

    摘要： An embodiment may include circuitry that may generate and/or use, at least in part, at least one descriptor to be associated with at least one packet. The at least one descriptor may specify at least one transmission time at which the at least one packet is to be transmitted. The at least one transmission time may be specified in the at least one descriptor in such a manner as to permit the at least one transmission time to be explicitly identified based at least in part upon the at least one descriptor. Many alternatives, modifications, and variations are possible without departing from this embodiment.

    摘要翻译： 实施例可以包括可以至少部分地生成和/或使用与至少一个分组相关联的至少一个描述符的电路。 所述至少一个描述符可以指定至少一个发送所述至少一个分组的传输时间。 至少一个发送时间可以以至少部分地基于至少一个描述符来明确地识别至少一个发送时间的方式在至少一个描述符中被指定。 在不脱离本实施例的情况下，可以进行许多替换，修改和变化。

    AUTOMATIC SWITCHING AND DEPLOYMENT OF SOFTWARE OR FIRMWARE BASED USB4 CONNECTION MANAGERS
    9.
    发明申请
    AUTOMATIC SWITCHING AND DEPLOYMENT OF SOFTWARE OR FIRMWARE BASED USB4 CONNECTION MANAGERS 审中-公开

    公开(公告)号：US20190317774A1

    公开(公告)日：2019-10-17

    申请号：US16456931

    申请日：2019-06-28

    申请人： Vinay Raghav ,  Prashant Sethi ,  Robert Gough ,  Reuven Rozic ,  Uri Soloveychik

    发明人： Vinay Raghav ,  Prashant Sethi ,  Robert Gough ,  Reuven Rozic ,  Uri Soloveychik

    IPC分类号： G06F9/4401 ,  G06F13/38 ,  G06F1/3215

    摘要： Automatic-switching and deployment of software (SW)- or firmware (FW)-based USB4 connection managers (CMs) and associated methods, apparatus, software and firmware. A handshake is defined between BIOS and an operating system (OS) to discover supported CM capability and dynamically switch from a FW CM to a SW CM and visa verse if there is a mismatch. In addition, a mechanism is defined to deploy the correct FW or SW CM driver based on class code, 2-part or 4-part ID. Support for continued USB4 operation during an OS upgrade or downgrade is provided, while ensuring that the best possible CM solution is used based on the advertised platform and OS capability. USB4 controllers support a pass-through mode under which the host controller FW redirects control packets sent between an SW CM and a USB4 fabric, and a FW CM mode under which control packets are communicated between the host controller FW and the USB4 fabric to configure USB4 peripheral devices and/or USB4 hubs in the USB4 fabric.

    CLOSED CHASSIS DEBUGGING THROUGH TUNNELING
    10.
    发明申请
    CLOSED CHASSIS DEBUGGING THROUGH TUNNELING 审中-公开

    公开(公告)号：US20200327041A1

    公开(公告)日：2020-10-15

    申请号：US16912545

    申请日：2020-06-25

    申请人： Gilad Shayevitz ,  Tsvika Kurts ,  Vladislav Kopzon ,  Reuven Rozic ,  Yaniv Hayat

    发明人： Gilad Shayevitz ,  Tsvika Kurts ,  Vladislav Kopzon ,  Reuven Rozic ,  Yaniv Hayat

    IPC分类号： G06F11/36 ,  G06F11/34 ,  G06F13/42 ,  G06F13/38

    摘要： A system can include a host machine connected to a device under test (DUT) by a serial link. The host machine can include a serial interface, such as a Thunderbolt interface, and a memory. The DUT can include a trace data source, a high-speed trace interface (HTI) to receive trace data from the trace data source, a serial interface (such as a Thunderbolt interface), and a PIPE interface connecting the HTI with the serial interface. The HTI is to send the trace data to the serial interface through the PIPE interface. The serial interface is to packetize the trace data into a conforming packet format, and send the trace data as a packet across the serial link to the host machine. The host machine can receive the trace data at the host-side serial interface, store the trace data in memory, and process the trace data for debugging the DUT.