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    Multicore DSP device having coupled subsystem memory buses for global DMA access
    1.
    发明授权
    Multicore DSP device having coupled subsystem memory buses for global DMA access 有权
    具有用于全局DMA访问的耦合子系统存储器总线的多核DSP设备

    公开(公告)号：US06892266B2

    公开(公告)日：2005-05-10

    申请号：US10008696

    申请日：2001-11-08

    申请人： Jay B. Reimer ,  Harland Glenn Hopkins ,  Tai H. Nguyen ,  Yi Luo ,  Kevin A. McGonagle ,  Jason A. Jones ,  Duy Q. Nguyen ,  Patrick J. Smith

    发明人： Jay B. Reimer ,  Harland Glenn Hopkins ,  Tai H. Nguyen ,  Yi Luo ,  Kevin A. McGonagle ,  Jason A. Jones ,  Duy Q. Nguyen ,  Patrick J. Smith

    IPC分类号： G06F9/30 ,  G06F13/16 ,  G06F13/28 ,  G06F13/362 ,  G06F15/78 ,  G06F13/14

    CPC分类号： G06F13/28

    摘要： A DSP device is disclosed having multiple DMA controllers with global DMA access to all volatile memory resources in the DSP device. In a preferred embodiment, each of the DMA controllers is coupled to each of the memory buses and is configured to control each of the memory buses. A memory bus multiplexer may be coupled between the subsystem memory bus and each of the DMA controllers, and an arbiter may be used to set the memory bus multiplexer so as to allow any one of the DMA controllers to control the memory bus. The memory bus may also be controlled by the host port interface via the memory bus multiplexer. A round-robin arbitration technique is used to provide each of the controllers and the host port interface fair access to the memory bus. This approach may advantageously provide increased flexibility in the use of DMA controllers to transfer data from place to place, with only a minimal increase in complexity.

    摘要翻译： 公开了具有多个DMA控制器的DSP设备，其全局DMA访问DSP设备中的所有易失性存储器资源。 在优选实施例中，每个DMA控制器耦合到每个存储器总线，并且被配置为控制每个存储器总线。 存储器总线多路复用器可以耦合在子系统存储器总线和每个DMA控制器之间，并且仲裁器可以用于设置存储器总线多路复用器，以便允许任何一个DMA控制器来控制存储器总线。 存储器总线也可以经由存储器总线多路复用器由主机端口接口来控制。 循环仲裁技术用于提供每个控制器和主机端口接口公平地访问存储器总线。 这种方法可以有利地提供使用DMA控制器将数据从一个地方传输到另一个地方的增加的灵活性，只有最小的复杂性增加。

    External bus arbitration technique for multicore DSP device
    2.
    发明授权
    External bus arbitration technique for multicore DSP device 有权
    多核DSP设备的外部总线仲裁技术

    公开(公告)号：US07006521B2

    公开(公告)日：2006-02-28

    申请号：US10007840

    申请日：2001-11-08

    申请人： Duy Q. Nguyen ,  Harland Glenn Hopkins ,  Jay B. Reimer ,  Yi Luo ,  Tai H. Nguyen ,  Kevin A. McGonagle

    发明人： Duy Q. Nguyen ,  Harland Glenn Hopkins ,  Jay B. Reimer ,  Yi Luo ,  Tai H. Nguyen ,  Kevin A. McGonagle

    IPC分类号： H04J3/02

    CPC分类号： G06F13/364

    摘要： A digital signal processing system includes multiple processor subsystems, an external input/output port (XPORT), and an XPORT arbiter. The processor subsystems each include a processor core and a DMA controller. The XPORT arbiter arbitrates between the processor cores and between the DMA controllers, and further arbitrates between processor control or DMA control of the XPORT. Upon a request signal from a DMA controller, the XPORT arbiter asserts a hold signal to the processor cores. The processor cores respond by asserting a hold acknowledge signal. A processor core will delay the hold acknowledge signal until through with the XPORT. The arbiter, then asserts a grant signal to the DMA controller requesting access. The arbiter may assert a grant signal to a processor core requesting access. However, the processor core's access will be stalled as long as the hold signal is asserted.

    摘要翻译： 数字信号处理系统包括多个处理器子系统，外部输入/输出端口（XPORT）和XPORT仲裁器。 处理器子系统各自包括处理器核心和DMA控制器。 XPORT仲裁器在处理器内核和DMA控制器之间进行仲裁，并进一步对XPORT的处理器控制或DMA控制进行仲裁。 根据来自DMA控制器的请求信号，XPORT仲裁器向处理器核心发出保持信号。 处理器核心通过置位保持确认信号来响应。 处理器内核将延迟保持确认信号，直到通过XPORT。 仲裁器然后向DMA控制器发出授权信号请求访问。 仲裁器可以向请求访问的处理器核心断言授权信号。 但是，只要保持信号有效，处理器核心的访问将被停止。

    Multicore DSP device having shared program memory with conditional write protection
    3.
    发明授权
    Multicore DSP device having shared program memory with conditional write protection 有权
    具有具有条件写保护功能的共享程序存储器的多核DSP设备

    公开(公告)号：US06895479B2

    公开(公告)日：2005-05-17

    申请号：US10008515

    申请日：2001-11-08

    申请人： Jay B. Reimer ,  Tai H. Nguyen ,  Yi Luo ,  Harland Glenn Hopkins ,  Dan K. Bui ,  Kevin A. McGonagle

    发明人： Jay B. Reimer ,  Tai H. Nguyen ,  Yi Luo ,  Harland Glenn Hopkins ,  Dan K. Bui ,  Kevin A. McGonagle

    IPC分类号： G06F12/14 ,  G06F9/00 ,  G06F11/00 ,  G06F11/26 ,  G06F12/00 ,  G06F15/177

    CPC分类号： G06F12/1433 ,  G06F11/2242 ,  G06F12/1491

    摘要： A multi-core digital signal processor is disclosed having a shared program memory with conditional write protection. In one embodiment, the digital signal processor includes a shared program memory, an emulation logic module, and multiple processor cores each coupled to the shared program memory by corresponding instruction buses. The emulation logic module preferably determines the operating modes of each of the processors, e.g., whether they are operating in a normal mode or an emulation mode. In the emulation mode, the emulation logic can alter the states of various processor hardware and the contents of various registers and memory. The instruction buses each include a read/write signal that, while their corresponding processor cores are in normal mode, is maintained in a read state. On the other hand, when the processor cores are in the emulation mode, the processor cores are allowed to determine the state of the instruction bus read/write signals. Each instruction bus read/write signal is preferably generated by a logic gate that prevents the processor core from affecting the read/write signal value in normal mode, but allows the processor core to determine the read/write signal value in emulation mode. In this manner, the logic gate prevents write operations to the shared program memory when the emulation logic de-asserts a signal indicative of emulation mode, and allows write operations to the shared program memory when the emulation logic asserts the signal indicative of emulation mode. The logic gate is preferably included in a bus interface module in each processor core.

    摘要翻译： 公开了具有具有条件写保护的共享程序存储器的多核数字信号处理器。 在一个实施例中，数字信号处理器包括共享程序存储器，仿真逻辑模块和多个处理器内核，每个核心通过相应的指令总线耦合到共享程序存储器。 仿真逻辑模块优选地确定每个处理器的操作模式，例如，它们是以正常模式还是仿真模式操作。 在仿真模式下，仿真逻辑可以改变各种处理器硬件的状态以及各种寄存器和存储器的内容。 指令总线各自包括读/写信号，其在相应的处理器核处于正常模式的同时被保持在读取状态。 另一方面，当处理器核心处于仿真模式时，允许处理器核心确定指令总线读/写信号的状态。 每个指令总线读/写信号优选地由逻辑门产生，该逻辑门防止处理器核在正常模式下影响读/写信号值，但允许处理器核确定仿真模式中的读/写信号值。 以这种方式，当仿真逻辑取消断言指示仿真模式的信号时，逻辑门防止对共享程序存储器的写操作，并且当仿真逻辑断言指示仿真模式的信号时，允许对共享程序存储器的写操作。 逻辑门优选地包括在每个处理器核心中的总线接口模块中。

    Shared program memory for use in multicore DSP devices
    4.
    发明授权
    Shared program memory for use in multicore DSP devices 有权
    用于多核DSP设备的共享程序存储器

    公开(公告)号：US06691216B2

    公开(公告)日：2004-02-10

    申请号：US10004492

    申请日：2001-10-24

    申请人： Kenneth C. Kelly ,  Irvinderpal S. Ghai ,  Jay B. Reimer ,  Tai Huu Nguyen ,  Harland Glenn Hopkins ,  Yi Luo ,  Jason A. T. Jones ,  Dan K. Bui ,  Patrick J. Smith ,  Kevin A. McGonagle

    发明人： Kenneth C. Kelly ,  Irvinderpal S. Ghai ,  Jay B. Reimer ,  Tai Huu Nguyen ,  Harland Glenn Hopkins ,  Yi Luo ,  Jason A. T. Jones ,  Dan K. Bui ,  Patrick J. Smith ,  Kevin A. McGonagle

    IPC分类号： G06F1578

    CPC分类号： G06F9/3802 ,  G06F9/3877 ,  G06F9/3879 ,  G06F9/3891 ,  G06F15/786 ,  Y02D10/13

    摘要： A multi-core DSP device includes a shared program memory to eliminate redundancy and thereby reduce the size and power consumption of the DSP device. Because each of the program cores typically executes the same software program, memory requirements may be reduced by having multiple processor cores share only a single copy of the software. Accordingly, a program memory couples to each of the processor cores by a corresponding instruction bus. Preferably the program memory services two or more instruction requests in each clock cycle. Data is preferably stored in separate memory arrays local to the processor core subsystems and accessible by the processor cores via a dedicated data bus. In one specific implementation, the program memory includes a wrapper that can perform one memory access in the first half of each clock cycle and a second memory access in the second half of each clock cycle. A designated set of instruction buses is allowed to arbitrate for only the first access, and the remaining instruction buses are allowed to arbitrate for only the second access. In this manner, a reduction in on-board memory requirements and associated power consumption may be advantageously reduced.

    摘要翻译： 多核DSP设备包括共享程序存储器以消除冗余，从而减小DSP设备的尺寸和功耗。 由于每个程序内核通常执行相同的软件程序，因此可以通过使多个处理器核心共享该软件的单个副本来减少内存需求。 因此，程序存储器通过相应的指令总线耦合到每个处理器核心。 优选地，程序存储器在每个时钟周期中服务两个或更多个指令请求。 数据优选地存储在处理器核心子系统本地的分开的存储器阵列中，并且可经由专用数据总线由处理器核心访问。 在一个具体实现中，程序存储器包括一个包装器，其可以在每个时钟周期的前半部分中执行一个存储器访问，并且在每个时钟周期的后半部分中执行第二存储器访问。 允许指定的一组指令总线仅对第一次访问进行仲裁，并且允许剩余的指令总线仅对第二次访问进行仲裁。 以这种方式，可以有利地减少车载存储器要求的降低和相关联的功率消耗。

    Method and system for data transmission
    5.
    发明授权
    Method and system for data transmission 有权
    数据传输方法和系统

    公开(公告)号：US08503564B2

    公开(公告)日：2013-08-06

    申请号：US12692202

    申请日：2010-01-22

    申请人： Bin Li ,  Yi Luo ,  Hui Shen

    发明人： Bin Li ,  Yi Luo ,  Hui Shen

    IPC分类号： H04B7/02 ,  H04L27/00

    CPC分类号： H04B7/0639

    摘要： A data transmission method, a communications system and related apparatuses are disclosed. The data transmission method includes the following steps: a transmitter obtains channel information corresponding to channels between the transmitter and several receivers; the transmitter obtains a control vector corresponding to a receiver according to the channel information; the transmitter modulates data to be transmitted by means of one-dimensional modulation to obtain modulated symbols; the transmitter processes the modulated symbols and the control vector to obtain transmitted data of each antenna; the transmitter transmits the transmitted data to the receiver; the receiver receives the transmitted data in a predetermined spatial direction of received symbol. The present invention also discloses a communications system and related apparatuses.

    摘要翻译： 公开了一种数据传输方法，通信系统及相关装置。 数据传输方法包括以下步骤：发射机获取与发射机和多个接收机之间的信道相对应的信道信息; 发射机根据信道信息获得对应于接收机的控制向量; 发射机通过一维调制器调制要传输的数据，以获得调制符号; 发射机处理调制符号和控制矢量以获得每个天线的发射数据; 发射机将发送的数据发送到接收机; 接收机以接收到的符号的预定空间方向接收发送的数据。 本发明还公开了一种通信系统及相关装置。

    Method and device for feeding back and receiving downlink channel information
    6.
    发明授权
    Method and device for feeding back and receiving downlink channel information 有权
    用于反馈和接收下行链路信道信息的方法和装置

    公开(公告)号：US08411727B2

    公开(公告)日：2013-04-02

    申请号：US12429409

    申请日：2009-04-24

    申请人： Luxi Yang ,  Daofeng Xu ,  Yongming Huang ,  Yi Luo

    发明人： Luxi Yang ,  Daofeng Xu ,  Yongming Huang ,  Yi Luo

    IPC分类号： H04B1/00

    CPC分类号： H04B7/06 ,  H04B7/0619 ,  H04L5/0026 ,  H04L5/0053 ,  H04L27/2647

    摘要： A method and a device for feeding back and receiving downlink channel information are disclosed, whereby spectrum utilization ratio of downlink channel information feedback is enhanced. According to the present invention, a wireless terminal superposes an uplink user information sequence with spectrum-spread downlink channel information before transmission. A network side de-spreads a received signal before estimating the downlink channel information, and then detects the user information sequence after subtracting the estimated downlink channel information from the received signal. An orthogonal code can be employed to spread the spectrum of the downlink channel information. The wireless terminal and base station use a plurality of antennas for transmission and reception.

    摘要翻译： 公开了一种用于反馈和接收下行链路信道信息的方法和装置，由此提高了下行链路信道反馈的频谱利用率。 根据本发明，无线终端在传输之前将上行用户信息序列与扩频下行信道信息叠加。 网络侧在估计下行链路信道信息之前解扩接收信号，然后在从接收到的信号中减去估计的下行链路信道信息之后检测用户信息序列。 可以采用正交码来扩展下行链路信道信息的频谱。 无线终端和基站使用多个天线进行发送和接收。

    Remote keyless entry system with two-way long range communication
    8.
    发明授权
    Remote keyless entry system with two-way long range communication 有权
    遥控无钥匙进入系统，双向远程通讯

    公开(公告)号：US08026793B2

    公开(公告)日：2011-09-27

    申请号：US10960657

    申请日：2004-10-07

    申请人： Yi Luo ,  Riad Ghabra ,  Qingfeng Tang

    发明人： Yi Luo ,  Riad Ghabra ,  Qingfeng Tang

    IPC分类号： H04Q1/00

    CPC分类号： B60R25/24 ,  G07C9/00309 ,  G07C2009/00793 ,  G07C2209/62 ,  H04B1/04

    摘要： Vehicle information (e.g., status information, calibratable parameters, or diagnostic data) is transmitted from a base station mounted in a vehicle to a portable RKE fob via a radio-frequency signal within a specified average field strength limit. A multi-byte vehicle message is formed and then coded into a multi-bit coded message. The multi-bit coded message is framed into a plurality of packets. The radio-frequency signal is wirelessly transmitted from the base station with a plurality of spaced packet windows having a predetermined duty cycle, each packet window including a respective one of the plurality of packets. The radio-frequency signal within each of the packet windows has a predetermined field strength greater than the average field strength limit and a substantially zero field strength between the packet windows. The predetermined duty cycle results in an actual average field strength for transmitting all of the packets not exceeding the average field strength limit.

    摘要翻译： 车辆信息（例如，状态信息，可校准参数或诊断数据）经由指定平均场强限度内的射频信号从安装在车辆中的基站发送到便携式RKE FOB。 形成多字节车辆消息，然后编码成多位编码消息。 多比特编码消息被构成多个分组。 射频信号是从具有预定占空比的多个间隔分组窗口从基站无线发送的，每个分组窗口包括多个分组中的相应一个分组。 每个分组窗口内的射频信号具有大于平均场强限度的预定场强和分组窗口之间基本为零的场强。 预定的占空比导致实际的平均场强，用于传送不超过平均场强极限的所有分组。