公开(公告)号：US08692528B2

公开(公告)日：2014-04-08

申请号：US12685962

申请日：2010-01-12

Applicant: Chua-Chin Wang ,  Shao-Fu Yen

Inventor： Chua-Chin Wang ,  Shao-Fu Yen

IPC: G05F1/00

CPC classification number: G05F1/56 ,  G05F1/575

Abstract: The present invention relates to a low dropout regulator, and more particularly to a low dropout regulator without load capacitor and ESR (equivalent series resistance) designed in response to the discharge curve of a Li-ion battery, includes an input terminal, a reference circuit, a power transfer element, a level regulating device, a regulating circuit, and a first N-type MOSFET. The regulating circuit detects a load change at an output terminal, amplifies the load change, and couples it to the level regulating device. The level regulating device receives and boosts a received signal and transmits the received signal to the power transfer element, so as to achieve the effect of controlling the power of a power supply.

Abstract translation: 低压差稳压器技术领域本发明涉及一种低压降稳压器，特别涉及一种无负载电容器的低压差稳压器和响应于锂离子电池的放电曲线设计的ESR（等效串联电阻），包括输入端子，参考电路 功率传递元件，电平调节器件，调节电路和第一N型MOSFET。 调节电路检测输出端子的负载变化，放大负载变化，并将其耦合到电平调节装置。 电平调节装置接收并升高接收的信号，并将接收的信号发送到电力传输元件，以实现控制电源的功率的效果。

公开(公告)号：US08339109B2

公开(公告)日：2012-12-25

申请号：US12727263

申请日：2010-03-19

Applicant: Chua-Chin Wang ,  Shao-Fu Yen ,  Jr-Shang Shie

Inventor： Chua-Chin Wang ,  Shao-Fu Yen ,  Jr-Shang Shie

IPC: H02J7/06 ,  H02J7/24

CPC classification number: H02J7/0086

Abstract: A charging circuit integrated into a chip, comprising a charging unit, a switch unit, a biasing unit, a voltage-dividing unit, and a comparing unit. The charging unit is connected between a power supply input and a load for outputting a constant current based on a constant bias voltage supplied by the power supply input in order to charge the load. The switch unit is connected between the charging unit and the power supply input for turning on or cutting off the charging unit. The voltage-dividing unit generates a first signal to the comparing unit according to a voltage of the load. The biasing unit outputs a second signal having a constant voltage to the comparing unit. The comparing unit compares the first signal with the second signal for cutting off or turning on the switch unit, bringing the charging unit to charge or stop charging the load, respectively.

Abstract translation: 集成在芯片中的充电电路，包括充电单元，开关单元，偏压单元，分压单元和比较单元。 充电单元连接在电源输入和用于输出恒定电流的负载之间，基于由电源输入提供的恒定偏置电压以对负载充电。 开关单元连接在充电单元和电源输入端之间，用于打开或切断充电单元。 分压单元根据负载的电压向比较单元产生第一信号。 偏置单元向比较单元输出具有恒定电压的第二信号。 比较单元将第一信号与用于切断或接通开关单元的第二信号进行比较，使充电单元分别对负载充电或停止充电。

公开(公告)号：US20110062922A1

公开(公告)日：2011-03-17

申请号：US12685962

申请日：2010-01-12

Applicant: Chua-Chin Wang ,  Shao-Fu Yen

Inventor： Chua-Chin Wang ,  Shao-Fu Yen

IPC: G05F1/10

CPC classification number: G05F1/56 ,  G05F1/575

Abstract: The present invention relates to a low dropout regulator, and more particularly to a low dropout regulator without load capacitor and ESR (equivalent series resistance) designed in response to the discharge curve of a Li-ion battery, includes an input terminal, a reference circuit, a power transfer element, a level regulating device, a regulating circuit, and a first N-type MOSFET. The regulating circuit detects a load change at an output terminal, amplifies the load change, and couples it to the level regulating device. The level regulating device receives and boosts a received signal and transmits the received signal to the power transfer element, so as to achieve the effect of controlling the power of a power supply.

Abstract translation: 低压差稳压器技术领域本发明涉及一种低压降稳压器，特别涉及一种无负载电容器的低压差稳压器和响应于锂离子电池的放电曲线设计的ESR（等效串联电阻），包括输入端子，参考电路 功率传递元件，电平调节器件，调节电路和第一N型MOSFET。 调节电路检测输出端子的负载变化，放大负载变化，并将其耦合到电平调节装置。 电平调节装置接收并升高接收的信号，并将接收的信号发送到电力传输元件，以实现控制电源的功率的效果。

公开(公告)号：US08498085B2

公开(公告)日：2013-07-30

申请号：US13589285

申请日：2012-08-20

Applicant: Federico A. Altolaguirre ,  Ming-Dou Ker ,  Chua-Chin Wang

Inventor： Federico A. Altolaguirre ,  Ming-Dou Ker ,  Chua-Chin Wang

IPC: H02H9/00 ,  H01C7/12 ,  H02H1/00 ,  H02H1/04 ,  H02H3/22

CPC classification number: H02H9/046

Abstract: An ESD protection circuit with leakage current reduction function includes a silicon controlled rectifier, a first CMOS inverter, a first transistor, a current mirror, a PMOS capacitor and a resistor. The first CMOS inverter electrically connects with the silicon controlled rectifier. The first transistor comprises a first end, a second end and a third end, wherein the first end electrically connects with the silicon controlled rectifier and the first CMOS inverter, and the current mirror electrically connects with the third end of the first transistor. The PMOS capacitor electrically connects with the current mirror, and the resistor electrically connects with the first CMOS inverter, the second end of the first transistor and the PMOS capacitor.

Abstract translation: 具有泄漏电流降低功能的ESD保护电路包括可控硅整流器，第一CMOS反相器，第一晶体管，电流镜，PMOS电容器和电阻器。 第一个CMOS反相器与可控硅整流器电连接。 第一晶体管包括第一端，第二端和第三端，其中第一端与可控硅整流器和第一CMOS反相器电连接，并且电流镜与第一晶体管的第三端电连接。 PMOS电容器与电流镜电连接，并且电阻器与第一CMOS反相器，第一晶体管的第二端和PMOS电容器电连接。

公开(公告)号：US08421506B2

公开(公告)日：2013-04-16

申请号：US12845231

申请日：2010-07-28

Applicant: Chua-Chin Wang ,  Ron-Chi Kuo ,  Jen-Wei Liu ,  Ming-Dou Ker

Inventor： Chua-Chin Wang ,  Ron-Chi Kuo ,  Jen-Wei Liu ,  Ming-Dou Ker

IPC: H03K3/00

CPC classification number: H03K19/00384 ,  G01R31/31715

Abstract: An output buffer with process and temperature compensation comprises an enable terminal, a clock generator, a PMOS threshold voltage detector, an NMOS threshold voltage detector, a first comparator, a second comparator, a first compensation code generator, a second compensation code generator and an output buffer stage, wherein the output buffer stage has an output stage, the output buffer stage means for controlling a drive current generated by the output stage, wherein the output stage has a first voltage output terminal, and the modulated drive current is capable of compensating slew rate of the first voltage output terminal.

Abstract translation: 具有过程和温度补偿的输出缓冲器包括使能端子，时钟发生器，PMOS阈值电压检测器，NMOS阈值电压检测器，第一比较器，第二比较器，第一补偿代码发生器，第二补偿代码发生器和 输出缓冲级，其中输出缓冲级具有输出级，输出缓冲级装置，用于控制由输出级产生的驱动电流，其中输出级具有第一电压输出端，并且调制驱动电流能够补偿 第一个电压输出端的转换速率。

公开(公告)号：US08339171B1

公开(公告)日：2012-12-25

申请号：US13194283

申请日：2011-07-29

Applicant: Chua-Chin Wang ,  Ron-Chi Kuo ,  Hsin-Yuan Tseng

Inventor： Chua-Chin Wang ,  Ron-Chi Kuo ,  Hsin-Yuan Tseng

IPC: H03K3/02

CPC classification number: G11C7/1057 ,  G01R31/2621 ,  G11C16/26 ,  G11C19/00 ,  H03K19/00384

Abstract: A threshold voltage detection circuit comprises a first inverter, a first transistor, a second transistor, a third transistor and a fourth transistor. The first inverter comprises a first terminal and a second terminal, a first electrode of the first transistor is electrically connected with the second terminal of the first inverter, a fourth electrode of the second transistor is electrically connected with the first terminal of the first inverter, a seventh electrode of the third transistor is electrically connected with the second terminal of the first inverter and the first electrode of the first transistor, a tenth electrode of the fourth transistor is electrically connected with a third electrode of the first transistor and a fifth electrode of the second transistor, and an eleventh electrode of the fourth transistor is electrically connected with a ninth electrode of the third transistor.

Abstract translation: 阈值电压检测电路包括第一反相器，第一晶体管，第二晶体管，第三晶体管和第四晶体管。 第一反相器包括第一端子和第二端子，第一晶体管的第一电极与第一反相器的第二端子电连接，第二晶体管的第四电极与第一反相器的第一端子电连接， 第三晶体管的第七电极与第一反相器的第二端子和第一晶体管的第一电极电连接，第四晶体管的第十电极与第一晶体管的第三电极电连接，第五电极的第五电极 第二晶体管和第四晶体管的第十一电极与第三晶体管的第九电极电连接。

公开(公告)号：US07932748B1

公开(公告)日：2011-04-26

申请号：US12640724

申请日：2009-12-17

Applicant: Ming-Dou Ker ,  Yan-Liang Lin ,  Chua-Chin Wang

Inventor： Ming-Dou Ker ,  Yan-Liang Lin ,  Chua-Chin Wang

IPC: H03K19/0175

CPC classification number: H03K19/018592 ,  H03K19/00384 ,  H03K19/018507

Abstract: A 2×VDD-tolerant input/output (I/O) buffer circuit with process, voltage, and temperature (PVT) compensation suitable for CMOS technology is disclosed. A 2×VDD-tolerant I/O buffer with a PVT compensation circuit is implemented with novel 2×VDD-tolerant logic gates. Output slew rate variations can be kept within smaller ranges to match maximum and minimum timing specifications. A 2×VDD tolerant logic circuit for implementing the I/O buffer is also disclosed.

公开(公告)号：US20110026175A1

公开(公告)日：2011-02-03

申请号：US12562426

申请日：2009-09-18

Applicant: Ming-Dou Ker ,  Chang-Tzu Wang ,  Chua-Chin Wang

Inventor： Ming-Dou Ker ,  Chang-Tzu Wang ,  Chua-Chin Wang

IPC: H02H9/04

CPC classification number: H01L27/0262 ,  H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to an electrostatic discharge protecting circuit with ultra-low standby leakage current for twice supply voltage tolerance. The electrostatic discharge protecting circuit of the invention includes a substrate driver, a third transistor, a start-up circuit, a RC circuit and a second resistor. The substrate driver has a first transistor and a second transistor in serious connection. The start-up circuit has a fourth transistor and a fifth transistor with diode-connected. The RC circuit has a first resistor, a sixth transistor and a seventh transistor in serious connection. Compared with the prior art, the electrostatic discharge protecting circuit with ultra-low standby leakage current for twice supply voltage tolerance of the invention with advantages of low standby leakage current, high ESD robustness, and no gate-oxide reliability issue is an excellent circuit solution for on-chip ESD protection design for mixed-voltage I/O buffers in nanometer CMOS technologies.

Abstract translation: 本发明涉及具有超低电源电压容限的超低待机漏电流的静电放电保护电路。 本发明的静电放电保护电路包括衬底驱动器，第三晶体管，启动电路，RC电路和第二电阻器。 衬底驱动器具有严格连接的第一晶体管和第二晶体管。 启动电路具有第四晶体管和具有二极管连接的第五晶体管。 RC电路具有严重连接的第一电阻器，第六晶体管和第七晶体管。 与现有技术相比，具有超低待机漏电电流的静电放电保护电路具有本发明两倍的电源电压公差，具有低待机漏电流，高ESD稳健性和无栅极氧化可靠性问题的优点，是一种极好的电路解决方案 用于纳米CMOS技术的混合电压I / O缓冲器的片上ESD保护设计。

公开(公告)号：US20060227594A1

公开(公告)日：2006-10-12

申请号：US11093766

申请日：2005-03-30

Applicant: Chua-Chin Wang ,  Tien-Hao Chen

Inventor： Chua-Chin Wang ,  Tien-Hao Chen

IPC: G11C11/00

CPC classification number: G11C11/413 ,  G11C8/08

Abstract: The invention relates to an integrated circuit memory unit comprising: a memory cell, a switched bulk DC voltage source and a plurality of wordline-controlled transistors. Each of wordline-controlled transistors has a bulk connected to the switched bulk DC voltage source. When the data bit is read from the memory cell or the data bit is written into the memory cell, the bulks of the wordline-controlled transistors are switched to a first voltage level from the switched bulk DC voltage source so as to increase the drain current and obtain faster operation speed. When in an idle mode, the bulks of the wordline-controlled transistors are switched to a second voltage level from the switched bulk DC voltage source so as to obtain higher threshold voltage and decrease the leakage current.

Abstract translation: 本发明涉及一种集成电路存储单元，包括：存储单元，开关体积直流电压源和多个字线控制晶体管。 字线控制晶体管中的每一个具有大量连接到开关体积直流电压源。 当从存储器单元读取数据位或将数据位写入存储单元时，将字线控制的晶体管的体积从切换体积直流电压源切换到第一电压电平，从而增加漏极电流 并获得更快的运行速度。 当处于空闲模式时，字线控制晶体管的体积从切换的体积直流电压源切换到第二电压电平，从而获得更高的阈值电压并减小漏电流。

公开(公告)号：US20060146972A1

公开(公告)日：2006-07-06

申请号：US11179847

申请日：2005-07-12

Applicant: Chua-Chin Wang ,  Ming-Kai Chang ,  Ling-Shiou Huang

Inventor： Chua-Chin Wang ,  Ming-Kai Chang ,  Ling-Shiou Huang

IPC: H03D3/24

CPC classification number: H03L7/085

Abstract: A method and a circuit for resolving the out-of-phase problem between a color burst signal and a sub-carrier signal of a television system. A delay means is used which leads to the synchronization of the color burst signal and the sub-carrier signal such that a subsequent color demodulator can demodulate correct color signals. Therefore, the locking of the two signals will be fastened without any excessively large circuit hardware.