公开(公告)号：US20120089360A1

公开(公告)日：2012-04-12

申请号：US13088880

申请日：2011-04-18

申请人： Chun-Chia Chen ,  Li-Ming Teng ,  Yu-Tsao Hsing

发明人： Chun-Chia Chen ,  Li-Ming Teng ,  Yu-Tsao Hsing

IPC分类号： G06F19/00

CPC分类号： G06F11/1441 ,  G11C29/16

摘要： The present invention discloses an algorithm integrating system and an integrating method thereof. The algorithm integrating system comprises a receiving module, an analyzing module, and a processing module. The receiving module receives at least one test algorithm. The analyzing module is connected to the receiving module and analyzes the at least one test algorithm to obtain at least one basic element from the at least one test algorithm. The processing module is connected to the analyzing module and screen out the at least one non-duplicate basic element based on the at least one basic element. Then, the processing module integrates the at least one non-duplicate basic element and generates a testing module.

摘要翻译： 本发明公开了一种算法集成系统及其集成方法。 算法集成系统包括接收模块，分析模块和处理模块。 接收模块接收至少一个测试算法。 所述分析模块连接到所述接收模块，并且分析所述至少一个测试算法以从所述至少一个测试算法中获得至少一个基本元素。 所述处理模块连接到所述分析模块，并基于所述至少一个基本元素屏蔽所述至少一个非重复的基本元素。 然后，处理模块集成至少一个非重复的基本元素，并生成测试模块。

公开(公告)号：US08744796B2

公开(公告)日：2014-06-03

申请号：US13088880

申请日：2011-04-18

申请人： Chun-Chia Chen ,  Li-Ming Teng ,  Yu-Tsao Hsing

发明人： Chun-Chia Chen ,  Li-Ming Teng ,  Yu-Tsao Hsing

IPC分类号： G06F11/00 ,  G06F11/14

CPC分类号： G06F11/1441 ,  G11C29/16

摘要： The present invention discloses an algorithm integrating system and an integrating method thereof. The algorithm integrating system comprises a receiving module, an analyzing module, and a processing module. The receiving module receives at least one test algorithm. The analyzing module is connected to the receiving module and analyzes the at least one test algorithm to obtain at least one basic element from the at least one test algorithm. The processing module is connected to the analyzing module and screen out the at least one non-duplicate basic element based on the at least one basic element. Then, the processing module integrates the at least one non-duplicate basic element and generates a testing module.

摘要翻译： 本发明公开了一种算法集成系统及其集成方法。 算法集成系统包括接收模块，分析模块和处理模块。 接收模块接收至少一个测试算法。 所述分析模块连接到所述接收模块，并且分析所述至少一个测试算法以从所述至少一个测试算法中获得至少一个基本元素。 所述处理模块连接到所述分析模块，并基于所述至少一个基本元素屏蔽所述至少一个非重复的基本元素。 然后，处理模块集成至少一个非重复的基本元素，并生成测试模块。

公开(公告)号：US08281199B2

公开(公告)日：2012-10-02

申请号：US12772407

申请日：2010-05-03

申请人： Yu-Tsao Hsing ,  Li-Ming Teng

发明人： Yu-Tsao Hsing ,  Li-Ming Teng

IPC分类号： G11C29/00 ,  G01R31/28 ,  G01R31/3187

CPC分类号： G11C29/1201 ,  G11C29/26 ,  G11C29/48 ,  G11C2029/0401

摘要： A hybrid self-test circuit structure comprises a plurality of input terminals and a plurality of output terminals for testing a plurality of memory units. The circuit structure comprises a first level functional unit for driving a plurality of first output terminals electrically coupled to the first level functional unit to output an output signal according to an external control signal transmitted from the outside; a plurality of second level functional units for receiving the output signal and generating a test signal according to the output signal and outputting the test signal to the memory units; a parallel interface parallelly installed between the first level functional unit and at least one of the second level functional units; and a serial interface serially installed between the first level functional unit and at least one of the second level functional units.

摘要翻译： 混合自检电路结构包括多个输入端和用于测试多个存储单元的多个输出端。 电路结构包括：第一级功能单元，用于驱动电耦合到第一级功能单元的多个第一输出端，​​以根据从外部发送的外部控制信号输出输出信号; 多个第二级功能单元，用于接收输出信号，并根据输出信号产生测试信号，并将测试信号输出到存储单元; 并行接口，并行地安装在所述第一级功能单元和所述第二级功能单元中的至少一个之间; 以及串行接口，串行地安装在第一级功能单元和至少一个第二级功能单元之间。

公开(公告)号：US20110267071A1

公开(公告)日：2011-11-03

申请号：US12772407

申请日：2010-05-03

申请人： Yu-Tsao Hsing ,  Li-Ming Teng

发明人： Yu-Tsao Hsing ,  Li-Ming Teng

IPC分类号： G01R31/02

CPC分类号： G11C29/1201 ,  G11C29/26 ,  G11C29/48 ,  G11C2029/0401

摘要： A hybrid self-test circuit structure comprises a plurality of input terminals and a plurality of output terminals for testing a plurality of memory units. The circuit structure comprises a first level functional unit for driving a plurality of first output terminals electrically coupled to the first level functional unit to output an output signal according to an external control signal transmitted from the outside; a plurality of second level functional units for receiving the output signal and generating a test signal according to the output signal and outputting the test signal to the memory units; a parallel interface parallelly installed between the first level functional unit and at least one of the second level functional units; and a serial interface serially installed between the first level functional unit and at least one of the second level functional units.

摘要翻译： 混合自检电路结构包括多个输入端和用于测试多个存储单元的多个输出端。 电路结构包括：第一级功能单元，用于驱动电耦合到第一级功能单元的多个第一输出端，​​以根据从外部发送的外部控制信号输出输出信号; 多个第二级功能单元，用于接收输出信号，并根据输出信号产生测试信号，并将测试信号输出到存储单元; 并行接口，并行地安装在所述第一级功能单元和所述第二级功能单元中的至少一个之间; 以及串行接口，串行地安装在第一级功能单元和至少一个第二级功能单元之间。

公开(公告)号：US20060252375A1

公开(公告)日：2006-11-09

申请号：US11203380

申请日：2005-08-12

申请人： Cheng-Wen Wu ,  Chih-Tsun Huang ,  Yu-Tsao Hsing

发明人： Cheng-Wen Wu ,  Chih-Tsun Huang ,  Yu-Tsao Hsing

IPC分类号： H04B17/00

CPC分类号： H04B17/0085 ,  G01R31/3025 ,  G01R31/303

摘要： The present invention discloses a probing system for integrated circuit devices, which transmits testing data between an automatic test equipment (ATE) and an integrated circuit device. The ATE includes a first transceiving module, and the integrated circuit device includes a core circuit, a built-in self-test (BIST) circuit electrically connected to the core circuit, a controller configured to control the operation of the BIST circuit, and a second transceiving module configured to exchange testing data with the first transceiving module. Preferably, the integrated circuit device further includes a clock generator and a power regulator electrically connected to the second transceiving module, wherein the ATE transmits a radio frequency signal via the first transceiving module, and the second transceiving module receives the radio frequency signal to drive the power regulator to generate power for the integrated circuit device to initiate the BIST circuit.

摘要翻译： 本发明公开了一种用于在自动测试设备（ATE）和集成电路设备之间传输测试数据的集成电路设备的探测系统。 ATE包括第一收发模块，集成电路装置包括核心电路，电连接到核心电路的内置自测试（BIST）电路，被配置为控制BIST电路的操作的控制器，以及 第二收发模块被配置为与第一收发模块交换测试数据。 优选地，集成电路装置还包括时钟发生器和电连接到第二收发模块的功率调节器，其中ATE经由第一收发模块发送射频信号，第二收发模块接收射频信号以驱动 电源调节器为集成电路器件产生电源以启动BIST电路。

公开(公告)号：US07904768B2

公开(公告)日：2011-03-08

申请号：US12114768

申请日：2008-05-03

申请人： Cheng-Wen Wu ,  Chih-Tsun Huang ,  Yu-Tsao Hsing

发明人： Cheng-Wen Wu ,  Chih-Tsun Huang ,  Yu-Tsao Hsing

IPC分类号： G01R31/28

CPC分类号： G01R31/303 ,  G01R31/2886 ,  G01R31/3025 ,  H04B17/0085

摘要： A probing system for an integrated circuit device, which transmits a testing data/signal between an automatic test equipment (ATE) and an integrated circuit device, is disclosed. The probing system includes a test head having a first transceiving module. There is a test station having a test unit coupled to the test head to perform a test operation. A communication module has a second transceiving module configured to exchange data with the first transceiving module in a wireless manner. There is an integrated circuit device having a core circuit being tested, and a test module having a self-test circuit coupled to the core circuit and the communication module for performing the core circuit self-testing.

摘要翻译： 公开了一种在自动测试设备（ATE）和集成电路设备之间传输测试数据/信号的集成电路设备的探测系统。 探测系统包括具有第一收发模块的测试头。 有一个测试站具有耦合到测试头的测试单元来执行测试操作。 通信模块具有被配置为以无线方式与第一收发模块交换数据的第二收发模块。 存在具有被测试的核心电路的集成电路器件，以及具有耦合到核心电路的自检电路和用于执行核心电路自检的通信模块的测试模块。

公开(公告)号：US20070232240A1

公开(公告)日：2007-10-04

申请号：US11761964

申请日：2007-06-12

申请人： Cheng-Wen Wu ,  Chih-Tsun Huang ,  Yu-Tsao Hsing

发明人： Cheng-Wen Wu ,  Chih-Tsun Huang ,  Yu-Tsao Hsing

IPC分类号： H04B1/38

CPC分类号： H04B17/0085 ,  G01R31/3025 ,  G01R31/303

摘要： The present invention discloses a probing system for integrated circuit devices, which transmits testing data between an automatic test equipment (ATE) and an integrated circuit device. The ATE includes a first transceiving module, and the integrated circuit device includes a core circuit, a built-in self-test (BIST) circuit electrically connected to the core circuit, a controller configured to control the operation of the BIST circuit, and a second transceiving module configured to exchange testing data with the first transceiving module. Preferably, the integrated circuit device further includes a clock generator and a power regulator electrically connected to the second transceiving module, wherein the ATE transmits a radio frequency signal via the first transceiving module, and the second transceiving module receives the radio frequency signal to drive the power regulator to generate power for the integrated circuit device to initiate the BIST circuit.

摘要翻译： 本发明公开了一种用于在自动测试设备（ATE）和集成电路设备之间传输测试数据的集成电路设备的探测系统。 ATE包括第一收发模块，集成电路装置包括核心电路，电连接到核心电路的内置自测试（BIST）电路，被配置为控制BIST电路的操作的控制器，以及 第二收发模块被配置为与第一收发模块交换测试数据。 优选地，集成电路装置还包括时钟发生器和电连接到第二收发模块的功率调节器，其中ATE经由第一收发模块发送射频信号，第二收发模块接收射频信号以驱动 电源调节器为集成电路器件产生电源以启动BIST电路。