公开(公告)号：US20120108026A1

公开(公告)日：2012-05-03

申请号：US12913041

申请日：2010-10-27

申请人： Chun-Feng NIEH ,  Ming-Huan TSAI ,  Wei-Han FAN ,  Yimin HUANG ,  Chun-Fai CHENG ,  Han-Ting TSAI ,  Chii-Ming WU

发明人： Chun-Feng NIEH ,  Ming-Huan TSAI ,  Wei-Han FAN ,  Yimin HUANG ,  Chun-Fai CHENG ,  Han-Ting TSAI ,  Chii-Ming WU

IPC分类号： H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of an integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite to the LDD region.

摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 在一个实施例中，该方法通过在器件的源极和漏极区域中形成掺杂区域和轻掺杂源极和漏极（LDD）区域来实现改进的控制。 掺杂区域注入与LDD区域相反的掺杂剂类型。

公开(公告)号：US20110212592A1

公开(公告)日：2011-09-01

申请号：US12713356

申请日：2010-02-26

申请人： Chun-Feng NIEH ,  Mao-Rong Yeh ,  Chun Hsiung Tsai ,  Chii-Ming Wu

发明人： Chun-Feng NIEH ,  Mao-Rong Yeh ,  Chun Hsiung Tsai ,  Chii-Ming Wu

IPC分类号： H01L21/336

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/26593 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/6659

摘要： A method of forming MOS transistor includes the steps of performing a pocket implantation process on a substrate having a gate stack, performing a co-implanted ion implantation process on the substrate at a temperature less than room temperature, performing a lightly doped source/drain implantation process on the substrate, and forming source and drain regions in the substrate, adjacent the gate stack.

摘要翻译： 一种形成MOS晶体管的方法包括以下步骤：在具有栅叠层的衬底上执行袋注入工艺，在低于室温的温度下在衬底上执行共注入离子注入工艺，执行轻掺杂源极/漏极注入 在衬底上形成源极和漏极区域，邻近栅极叠层。

公开(公告)号：US20130137238A1

公开(公告)日：2013-05-30

申请号：US13407465

申请日：2012-02-28

申请人： Chun-Feng NIEH ,  Huicheng CHANG ,  Hung-Ta LIN

发明人： Chun-Feng NIEH ,  Huicheng CHANG ,  Hung-Ta LIN

IPC分类号： H01L21/762

CPC分类号： H01L21/76224

摘要： Provided is a method of fabricating a semiconductor device. The method includes forming a buffer layer over a surface of a silicon substrate. The method further includes forming openings that extend into the buffer layer. The method includes forming a shallow trench isolation (STI) structures in each of the openings. The method includes removing a predetermined amount of a top surface of the buffer layer relative to a top surface of the STI structures. The method includes forming an insulator layer over the top surface of the buffer layer and forming a channel layer over the insulator layer.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在硅衬底的表面上形成缓冲层。 该方法还包括形成延伸到缓冲层中的开口。 该方法包括在每个开口中形成浅沟槽隔离（STI）结构。 该方法包括相对于STI结构的顶表面去除预定量的缓冲层的顶表面。 该方法包括在缓冲层的顶表面上形成绝缘体层，并在绝缘体层上形成沟道层。

公开(公告)号：US20110111571A1

公开(公告)日：2011-05-12

申请号：US12616406

申请日：2009-11-11

申请人： Chun Hsiung TSAI ,  Chun-Feng NIEH ,  Da-Wen LIN ,  Chien-Tai CHAN

发明人： Chun Hsiung TSAI ,  Chun-Feng NIEH ,  Da-Wen LIN ,  Chien-Tai CHAN

IPC分类号： H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming ultra-shallow p-type lightly doped drain (LDD) regions of a PMOS transistor in a surface of a substrate includes the steps of providing a gaseous mixture of an inert gas, a boron-containing source, and an optional carbon-containing source, wherein the concentration of the gaseous mixture is at least 99.5% dilute with the inert gas and the optional carbon-containing source, if present, forming the gaseous mixture into a plasma, and forming the LDD regions, wherein the forming step includes plasma-doping the boron into the substrate using the plasma. N-type pocket regions are formed in the substrate underneath and adjacent to the LDD regions, wherein for a PMOS transistor having a threshold voltage of 100 mV, the n-type pocket regions include phosphorous impurities at a dopant concentration of less than 6.0×1018 atoms/cm3 or a proportionately lower/higher dopant concentration for a lower/higher threshold voltage.

摘要翻译： 在衬底的表面中形成PMOS晶体管的超浅p型轻掺杂漏极（LDD）区域的方法包括以下步骤：提供惰性气体，含硼源和任选的碳的气态混合物 其中气态混合物的浓度与惰性气体和任选的含碳源（如果存在）一起稀释至少99.5％，将气态混合物形成等离子体，并形成LDD区域，其中形成步骤 包括使用等离子体将硼等离子体掺杂到衬底中。 在LDD区域下方并与LDD区域相邻的衬底中形成N型口袋区域，其中对于阈值电压为100mV的PMOS晶体管，n型袋区域包括掺杂剂浓度小于6.0×1018的磷杂质 原子/ cm 3或低/高阈值电压的比例较低/较高掺杂剂浓度。

公开(公告)号：US20120100686A1

公开(公告)日：2012-04-26

申请号：US12908640

申请日：2010-10-20

申请人： Wei-Yuan LU ,  Li-Ping HUANG ,  Mao-Rong YEH ,  Chun-Feng NIEH

发明人： Wei-Yuan LU ,  Li-Ping HUANG ,  Mao-Rong YEH ,  Chun-Feng NIEH

IPC分类号： H01L21/336

CPC分类号： H01L21/26593 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66545

摘要： A method of forming ultra-shallow lightly doped source/drain (LDD) regions of a CMOS transistor in a surface of a substrate includes the steps of providing a semiconductor substrate, providing a gate stack on the semiconductor substrate, performing a low temperature pocket implantation process on the substrate, performing a low temperature co-implanted ion implantation process on the substrate, and/or performing a low temperature lightly doped source/drain implantation process on the substrate.

摘要翻译： 在衬底的表面中形成CMOS晶体管的超浅掺杂光源/漏极（LDD）区域的方法包括以下步骤：提供半导体衬底，在半导体衬底上提供栅极堆叠，执行低温腔体注入 在衬底上进行处理，在衬底上执行低温共注入离子注入工艺，和/或在衬底上执行低温轻掺杂源极/漏极注入工艺。