公开(公告)号：US10163724B2

公开(公告)日：2018-12-25

申请号：US13409999

申请日：2012-03-01

申请人： Pai-Chieh Wang ,  Yimin Huang

发明人： Pai-Chieh Wang ,  Yimin Huang

IPC分类号： H01L21/8238

摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved protection for the bottom portion of the gate structure. In some embodiments, the method achieves improved protection for gate structure bottom by forming a recess on either side of the gate structure and placing spacers on the side walls of the gate structure, so that the spacers protect the portion of the gate structure below the gate dielectric layer.

公开(公告)号：US09269833B2

公开(公告)日：2016-02-23

申请号：US13303096

申请日：2011-11-22

申请人： Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang

发明人： Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang

IPC分类号： H01L29/94 ,  H01L27/06 ,  H01L27/08 ,  H01L49/02

CPC分类号： H01L29/94 ,  H01L27/0629 ,  H01L27/0811 ,  H01L28/20

摘要： Methods and apparatus for hybrid MOS capacitors in replacement gate process. A method is disclosed including patterning a gate dielectric layer and a polysilicon gate layer to form a polysilicon gate region over a substrate; forming an inter-level dielectric layer over the substrate and surrounding the polysilicon gate region; defining polysilicon resistor regions each containing at least one portion of the polysilicon gate region and not containing at least one other portion of the polysilicon gate region, forming dummy gate regions removing the dummy gate regions and the gate dielectric layer underneath the dummy gate regions to leave trenches; and forming high-k metal gate devices in the trenches. A capacitor region including a high-k metal gate and a polysilicon gate next to the high-k metal gate is disclosed. Additional hybrid capacitor apparatuses are disclosed.

摘要翻译： 替代栅极工艺中混合MOS电容器的方法和装置。 公开了一种方法，其包括图案化栅极电介质层和多晶硅栅极层以在衬底上形成多晶硅栅极区域; 在所述衬底上形成层间电介质层并围绕所述多晶硅栅极区域; 限定多晶硅电阻器区域，每个多晶硅电阻器区域包含多晶硅栅极区域的至少一部分并且不包含多晶硅栅极区域的至少一个其他部分，形成伪栅极区域，去除伪栅极区域和伪栅极区域下方的栅极介电层，以留下 沟渠 并在沟槽中形成高k金属栅极器件。 公开了一种包括高k金属栅极和与高k金属栅极相邻的多晶硅栅极的电容器区域。 公开了另外的混合电容器装置。

公开(公告)号：US08857739B2

公开(公告)日：2014-10-14

申请号：US13323754

申请日：2011-12-12

申请人： Yimin Huang ,  Shaun Sullivan ,  Brian Finstad ,  Alexander Haplau-Colan

发明人： Yimin Huang ,  Shaun Sullivan ,  Brian Finstad ,  Alexander Haplau-Colan

IPC分类号： B05B7/10 ,  F02C1/00 ,  F02G3/00 ,  F23R3/14 ,  F23R3/28 ,  F23R3/46

CPC分类号： F23R3/14 ,  F23R3/283 ,  F23R3/286 ,  F23R3/46

摘要： A combustor for a gas turbine engine is disclosed which is able to operate with high combustion efficiency, and low nitrous oxide emissions during gas turbine operations. The combustor consists of a can-type configuration which combusts fuel premixed with air and delivers the hot gases to a turbine. Fuel is premixed with air through a swirler and is delivered to the combustor with a high degree of swirl motion about a central axis. This swirling mixture of reactants is conveyed downstream through a flow path that expands; the mixture reacts, and establishes an upstream central recirculation flow along the central axis. A cooling assembly is located on the swirler co-linear with the central axis in which cooler air is conveyed into the prechamber between the recirculation flow and the swirler surface.

摘要翻译： 公开了一种用于燃气涡轮发动机的燃烧器，其能够在燃气轮机操作期间以高燃烧效率和低氧化亚氮排放进行操作。 燃烧器由罐型构成，其燃烧与空气预混合的燃料并将热气体输送到涡轮机。 燃料通过旋流器与空气预混合并且以围绕中心轴线的高度漩涡运动输送到燃烧器。 反应物的这种旋转混合物通过膨胀的流动路径向下游传送; 混合物反应，并建立沿中心轴的上游中央再循环流。 冷却组件位于与中心轴线共线的旋流器上，其中较冷的空气被输送到再循环流和旋流器表面之间的预燃室中。

公开(公告)号：US08680625B2

公开(公告)日：2014-03-25

申请号：US12905579

申请日：2010-10-15

申请人： Wei-Han Fan ,  Yu-Hsien Lin ,  Yimin Huang ,  Ming-Huan Tsai ,  Hsueh-Chang Sung ,  Chun-Fai Cheng

发明人： Wei-Han Fan ,  Yu-Hsien Lin ,  Yimin Huang ,  Ming-Huan Tsai ,  Hsueh-Chang Sung ,  Chun-Fai Cheng

IPC分类号： H01L27/088

CPC分类号： H01L29/165 ,  H01L21/28123 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： An exemplary semiconductor device is described, which includes a semiconductor substrate having an active region and an isolation region. The active region has a first edge which interfaces with the isolation region. A gate structure formed on the semiconductor substrate. A spacer element abuts the gate structure and overlies the first edge. In an embodiment, the isolation region is an STI structure. An epitaxy region may be formed adjacent the spacer. In embodiments, this epitaxy region is facet-free.

摘要翻译： 描述了一种示例性的半导体器件，其包括具有有源区和隔离区的半导体衬底。 有源区域具有与隔离区域相接合的第一边缘。 形成在半导体衬底上的栅极结构。 间隔元件邻接栅极结构并覆盖在第一边缘上。 在一个实施例中，隔离区域是STI结构。 可以在间隔物附近形成外延区域。 在实施例中，该外延区域是无面的。

公开(公告)号：US08455952B2

公开(公告)日：2013-06-04

申请号：US12951676

申请日：2010-11-22

申请人： Yun Jing Lin ,  Wei-Han Fan ,  Yu-Hsien Lin ,  Yimin Huang

发明人： Yun Jing Lin ,  Wei-Han Fan ,  Yu-Hsien Lin ,  Yimin Huang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/41783 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/78

摘要： The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. In an embodiment, the first spacer element includes silicon nitride. A second spacer element is adjacent the first spacer element. In an embodiment, the second spacer element includes silicon oxide. A raised source and a first raised drain is provided laterally contacting sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element.

摘要翻译： 本公开描述了一种包括半导体衬底和设置在半导体衬底上的栅极堆叠的半导体器件。 第一间隔元件设置在邻接第一栅极叠层的基板上。 在一个实施例中，第一间隔元件包括氮化硅。 第二间隔元件与第一间隔元件相邻。 在一个实施例中，第二间隔元件包括氧化硅。 凸起的源和第一升高的漏极被设置成横向接触第二间隔元件的侧壁。 在一个实施例中，触点与第二间隔元件直接接触。

公开(公告)号：US20120126331A1

公开(公告)日：2012-05-24

申请号：US12951676

申请日：2010-11-22

申请人： Yun Jing Lin ,  Wei-Han Fan ,  Yu-Hsien Lin ,  Yimin Huang

发明人： Yun Jing Lin ,  Wei-Han Fan ,  Yu-Hsien Lin ,  Yimin Huang

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L29/772

CPC分类号： H01L29/41783 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/78

摘要： The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. In an embodiment, the first spacer element includes silicon nitride. A second spacer element is adjacent the first spacer element. In an embodiment, the second spacer element includes silicon oxide. A raised source and a first raised drain is provided laterally contacting sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element.

摘要翻译： 本公开描述了一种包括半导体衬底和设置在半导体衬底上的栅极堆叠的半导体器件。 第一间隔元件设置在邻接第一栅极叠层的基板上。 在一个实施例中，第一间隔元件包括氮化硅。 第二间隔元件与第一间隔元件相邻。 在一个实施例中，第二间隔元件包括氧化硅。 凸起的源和第一升高的漏极被设置成横向接触第二间隔元件的侧壁。 在一个实施例中，触点与第二间隔元件直接接触。

公开(公告)号：US20120100681A1

公开(公告)日：2012-04-26

申请号：US12981610

申请日：2010-12-30

申请人： Ziwei FANG ,  Jeff J. XU ,  Ming-Jie HUANG ,  Yimin HUANG ,  Zhiqiang WU ,  Min CAO

发明人： Ziwei FANG ,  Jeff J. XU ,  Ming-Jie HUANG ,  Yimin HUANG ,  Zhiqiang WU ,  Min CAO

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/02057 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

摘要： An integrated circuit device and method for manufacturing the integrated circuit device provide improved control over a shape of a trench for forming the source and drain features of integrated circuit device, by forming a second doped region in a first doped region and removing the first and the second doped regions by a first and a second wet etching processes.

摘要翻译： 用于制造集成电路器件的集成电路器件和方法通过在第一掺杂区域中形成第二掺杂区域并且去除第一和第二掺杂区域，从而提供对用于形成集成电路器件的源极和漏极特征的沟槽形状的改进的控制 第二掺杂区域通过第一和第二湿蚀刻工艺。

公开(公告)号：US20050263876A1

公开(公告)日：2005-12-01

申请号：US11196038

申请日：2005-08-02

申请人： Tri-Rung Yew ,  Yimin Huang ,  Water Lur ,  Shih-Wei Sun

发明人： Tri-Rung Yew ,  Yimin Huang ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L21/768 ,  H01L23/12 ,  H01L23/532

CPC分类号： H01L21/7681 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.

摘要翻译： 提供了一种改进的双镶嵌结构，用于集成电路中多级互连的布线结构。 在这种双镶嵌结构中，使用低K（低介电常数）介电材料来形成IC器件中的金属互连之间的二电层和蚀刻停止层。 利用该特征，双镶嵌结构可以防止在其中发生高的寄生电容，否则会对通过金属互连传输的信号造成较大的RC延迟，从而降低IC器件的性能。 利用双镶嵌结构，可以减少这种寄生电容，从而确保IC器件的性能。

公开(公告)号：US06794752B2

公开(公告)日：2004-09-21

申请号：US09864055

申请日：2001-05-23

申请人： Ellis Lee ,  Yimin Huang ,  Tri-Rung Yew

发明人： Ellis Lee ,  Yimin Huang ,  Tri-Rung Yew

IPC分类号： H01L2348

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/45 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： An bonding pad structure has a passivation layer over a copper layer having a pad window to expose a portion of the copper layer, a barrier layer conformal to a profile of the pad window, and an aluminum pad located in the pad window. The metal layer can be an aluminum, aluminum alloy or aluminum dominated layer for providing a better adhesion property between the copper layer and the bonding wire.

摘要翻译： 焊盘结构在铜层上具有钝化层，其具有用于暴露铜层的一部分的焊盘窗口，与焊盘窗口的轮廓保形的阻挡层和位于焊盘窗口中的铝焊盘。 金属层可以是铝，铝合金或铝主导层，用于在铜层和接合线之间提供更好的粘合性能。

公开(公告)号：US06265780B1

公开(公告)日：2001-07-24

申请号：US09203035

申请日：1998-12-01

申请人： Tri-Rung Yew ,  Yimin Huang ,  Water Lur ,  Shih-Wei Sun

发明人： Tri-Rung Yew ,  Yimin Huang ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L2348

CPC分类号： H01L21/76832 ,  H01L21/7681 ,  H01L21/76813 ,  H01L21/76835

摘要： An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the dielectric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.

摘要翻译： 提供了一种改进的双镶嵌结构，用于集成电路中多级互连的布线结构。 在这种双镶嵌结构中，使用低K（低介电常数）介电材料来形成IC器件中的金属互连之间的介电层和蚀刻停止层。 利用该特征，双镶嵌结构可以防止在其中发生高的寄生电容，否则会对通过金属互连传输的信号造成较大的RC延迟，从而降低IC器件的性能。 利用双镶嵌结构，可以减少这种寄生电容，从而确保IC器件的性能。