公开(公告)号：US08535998B2

公开(公告)日：2013-09-17

申请号：US12720075

申请日：2010-03-09

Applicant: Fung Ka Hing ,  Haiting Wang ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

Inventor： Fung Ka Hing ,  Haiting Wang ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

IPC: H01L21/338

CPC classification number: H01L29/7833 ,  H01L21/76834 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/7836

Abstract: The present disclosure discloses an exemplary method for fabricating a gate structure comprising depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a sacrificial layer; surrounding the sacrificial layer with a nitrogen-containing dielectric layer; surrounding the nitrogen-containing dielectric layer with an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer; removing the sacrificial layer to form an opening in the nitrogen-containing dielectric layer; and depositing a gate dielectric; and depositing a gate electrode.

Abstract translation: 本公开公开了一种用于制造栅极结构的示例性方法，其包括在衬底上沉积和图案化虚拟氧化物层和伪栅极电极层; 围绕所述虚拟氧化物层和所述伪栅极电极层，具有牺牲层; 用含氮介电层围绕牺牲层; 用层间介质层包围含氮介电层; 去除所述伪栅电极层; 去除虚拟氧化物层; 去除所述牺牲层以在所述含氮介电层中形成开口; 并沉积栅极电介质; 并沉积栅电极。

公开(公告)号：US20130187221A1

公开(公告)日：2013-07-25

申请号：US13356207

申请日：2012-01-23

Applicant: Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai ,  Wei-Ching Wang ,  Ming-Shuan Li ,  Hsueh-Jen Yang ,  Kuan-Chung Chen

Inventor： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai ,  Wei-Ching Wang ,  Ming-Shuan Li ,  Hsueh-Jen Yang ,  Kuan-Chung Chen

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7849 ,  B82Y10/00 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/32 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7613 ,  H01L29/7843 ,  H01L29/7848

Abstract: A method of forming a semiconductor device includes performing a first pre-amorphous implantation process on a substrate, where the substrate has a gate stack. The method further includes forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate, and performing a second annealing process on the substrate and the second stress film.

Abstract translation: 形成半导体器件的方法包括在衬底上执行第一预非晶体注入工艺，其中衬底具有栅叠层。 该方法还包括在衬底上形成第一应力膜。 该方法还包括对基板和第一应力膜执行第一退火处理。 该方法还包括在退火的衬底上执行第二预非晶体注入工艺，在衬底上形成第二应力膜，并对衬底和第二应力膜执行第二退火处理。

公开(公告)号：US08828817B2

公开(公告)日：2014-09-09

申请号：US13356207

申请日：2012-01-23

Applicant: Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai ,  Wei-Ching Wang ,  Ming-Shuan Li ,  Hsueh-Jen Yang ,  Kuan-Chung Chen

Inventor： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai ,  Wei-Ching Wang ,  Ming-Shuan Li ,  Hsueh-Jen Yang ,  Kuan-Chung Chen

IPC: H01L21/8238

CPC classification number: H01L29/7849 ,  B82Y10/00 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/32 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7613 ,  H01L29/7843 ,  H01L29/7848

Abstract: A method of forming a semiconductor device includes performing a first pre-amorphous implantation process on a substrate, where the substrate has a gate stack. The method further includes forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate, and performing a second annealing process on the substrate and the second stress film.

Abstract translation: 形成半导体器件的方法包括在衬底上执行第一预非晶体注入工艺，其中衬底具有栅叠层。 该方法还包括在衬底上形成第一应力膜。 该方法还包括对基板和第一应力膜执行第一退火处理。 该方法还包括在退火的衬底上执行第二预非晶体注入工艺，在衬底上形成第二应力膜，并对衬底和第二应力膜执行第二退火处理。

公开(公告)号：US08053344B1

公开(公告)日：2011-11-08

申请号：US12886743

申请日：2010-09-21

Applicant: Ka-Hing Fung ,  Wei-Yuan Lu ,  Han-Ting Tsai

Inventor： Ka-Hing Fung ,  Wei-Yuan Lu ,  Han-Ting Tsai

IPC: H01L29/00

CPC classification number: H01L21/2257 ,  H01L29/41783 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. At least one silicon-containing layer is formed in source/drain (S/D) regions adjacent to sidewalls of the gate structure. An N-type doped silicon-containing layer is formed over the at least one silicon-containing layer. The N-type doped silicon-containing layer has an N-type dopant concentration higher than that of the at least one silicon-containing layer. The N-type doped silicon-containing layer is annealed so as to drive N-type dopants of the N-type doped silicon-containing layer to the S/D regions.

Abstract translation: 形成集成电路的方法包括在衬底上形成栅极结构。 在与栅极结构的侧壁相邻的源极/漏极（S / D）区域中形成至少一个含硅层。 在至少一个含硅层上形成N型掺杂含硅层。 N型掺杂含硅层的N型掺杂剂浓度高于至少一种含硅层。 对N型掺杂含硅层进行退火，以将N型掺杂含硅层的N型掺杂剂驱动到S / D区。

公开(公告)号：US08754477B2

公开(公告)日：2014-06-17

申请号：US13277872

申请日：2011-10-20

Applicant: Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai ,  Wei-Ching Wang ,  Ming-Shuan Li ,  Hsueh-Jen Yang ,  Kuan-Chung Chen

Inventor： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai ,  Wei-Ching Wang ,  Ming-Shuan Li ,  Hsueh-Jen Yang ,  Kuan-Chung Chen

IPC: H01L27/12 ,  H01L21/336

CPC classification number: H01L21/26506 ,  H01L21/2658 ,  H01L21/26593 ,  H01L21/324 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/78654

Abstract: A method of fabricating and a semiconductor device with multiple dislocation structures is disclosed. The exemplary semiconductor device includes gate structure overlying a top surface of a semiconductor substrate and a first gate spacer disposed on a sidewall of the gate structure and overlying the top surface of the substrate. The semiconductor device further includes a crystallized semiconductor material overlying the top surface of the semiconductor substrate and adjacent to a sidewall of the first gate spacer. The semiconductor device further includes a second gate spacer disposed on the sidewall of the first gate spacer and overlying the crystallized semiconductor material. The semiconductor device further includes a first stressor region disposed in the semiconductor substrate and a second stressor region disposed in the semiconductor substrate and in the crystallized semiconductor material.

Abstract translation: 公开了一种制造方法和具有多个位错结构的半导体器件。 示例性半导体器件包括覆盖半导体衬底的顶表面的栅极结构和设置在栅极结构的侧壁上且覆盖衬底顶表面的第一栅极间隔。 半导体器件还包括结晶半导体材料，其覆盖半导体衬底的顶表面并与第一栅极间隔物的侧壁相邻。 半导体器件还包括设置在第一栅极间隔物的侧壁上并覆盖结晶的半导体材料的第二栅极间隔物。 半导体器件还包括设置在半导体衬底中的第一应力区域和设置在半导体衬底和晶体化半导体材料中的第二应力区域。

公开(公告)号：US08455859B2

公开(公告)日：2013-06-04

申请号：US12571604

申请日：2009-10-01

Applicant: Ming-Huan Tsai ,  Han-Ting Tsai

Inventor： Ming-Huan Tsai ,  Han-Ting Tsai

IPC: H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC classification number: H01L21/823418 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833 ,  H01L29/7848

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, a gate structure disposed on a surface of the substrate, and strained structures disposed in the substrate at either side of the gate structure and formed of a semiconductor material different from the semiconductor substrate. Each strained structure has a cross-sectional profile that includes a first portion that extends from the surface of substrate and a second portion that tapers from the first portion at an angle ranging from about 50° to about 70°. The angle is measured with respect to an axis parallel to the surface of the substrate.

Abstract translation: 本公开提供一种半导体器件，其包括半导体衬底，设置在衬底的表面上的栅极结构以及设置在栅极结构的任一侧的衬底中的应变结构，并且由与半导体衬底不同的半导体材料形成。 每个应变结构具有横截面轮廓，该截面轮廓包括从基底表面延伸的第一部分和从第一部分以约50°至约70°的角度逐渐变细的第二部分。 角度相对于平行于基板表面的轴线被测量。

公开(公告)号：US20130099294A1

公开(公告)日：2013-04-25

申请号：US13280094

申请日：2011-10-24

Applicant: Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai

Inventor： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/26506 ,  H01L21/26593 ,  H01L21/76232 ,  H01L29/045 ,  H01L29/7833 ,  H01L29/7847

Abstract: A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET), which includes forming a first dislocation plane adjacent to a gate electrode of the MOSFET, and forming a second dislocation plane adjacent to the gate electrode of the MOSFET. The first and the second dislocation planes are on a same side of the gate electrode, and extend into source/drain regions of the MOSFET.

Abstract translation: 一种方法包括形成金属氧化物半导体场效应晶体管（MOSFET），其包括形成与MOSFET的栅电极相邻的第一位错面，并形成与MOSFET的栅电极相邻的第二位错面。 第一和第二位错平面位于栅电极的同一侧，并延伸到MOSFET的源/漏区。

公开(公告)号：US08405160B2

公开(公告)日：2013-03-26

申请号：US12787972

申请日：2010-05-26

Applicant: Chun-Fai Cheng ,  Fung Ka Hing ,  Ming-Huan Tsai ,  Chun-Feng Nieh ,  Yimin Huang ,  Han-Ting Tsai ,  Haiting Wang

Inventor： Chun-Fai Cheng ,  Fung Ka Hing ,  Ming-Huan Tsai ,  Chun-Feng Nieh ,  Yimin Huang ,  Han-Ting Tsai ,  Haiting Wang

IPC: H01L27/088 ,  H01L21/8238

CPC classification number: H01L29/7848 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/30608 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a silicon substrate. The semiconductor device includes first and second regions that are disposed in the substrate. The first and second regions have a silicon compound material. The semiconductor device includes first and second source/drain structures that are partially disposed in the first and second regions, respectively. The semiconductor device includes a first gate that is disposed over the substrate. The first gate has a first proximity to the first region. The semiconductor device includes a second gate that is disposed over the substrate. The second gate has a second proximity to the second region. The second proximity is different from the first proximity. The first source/drain structure and the first gate are portions of a first transistor, and the second source/drain structure and the second gate are portions of a second transistor.

Abstract translation: 本发明提供一种半导体器件。 半导体器件包括硅衬底。 半导体器件包括设置在衬底中的第一和第二区域。 第一和第二区域具有硅化合物材料。 半导体器件包括分别部分地设置在第一和第二区域中的第一和第二源极/漏极结构。 半导体器件包括设置在衬底上的第一栅极。 第一个门第一个靠近第一个地区。 半导体器件包括设置在衬底上的第二栅极。 第二个门第二个靠近第二个区域。 第二接近度与第一接近度不同。 第一源极/漏极结构和第一栅极是第一晶体管的部分，并且第二源极/漏极结构和第二栅极是第二晶体管的部分。

公开(公告)号：US20120070954A1

公开(公告)日：2012-03-22

申请号：US13274558

申请日：2011-10-17

Applicant: Ka-Hing FUNG ,  Wei-Yuan LU ,  Han-Ting TSAI

Inventor： Ka-Hing FUNG ,  Wei-Yuan LU ,  Han-Ting TSAI

IPC: H01L21/336

CPC classification number: H01L21/2257 ,  H01L29/41783 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. At least one silicon-containing layer is formed in source/drain (S/D) regions adjacent to sidewalls of the gate structure. An N-type doped silicon-containing layer is formed over the at least one silicon-containing layer. The N-type doped silicon-containing layer has an N-type dopant concentration higher than that of the at least one silicon-containing layer. The N-type doped silicon-containing layer is annealed so as to drive N-type dopants of the N-type doped silicon-containing layer to the S/D regions.

Abstract translation: 形成集成电路的方法包括在衬底上形成栅极结构。 在与栅极结构的侧壁相邻的源极/漏极（S / D）区域中形成至少一个含硅层。 在至少一个含硅层上形成N型掺杂的含硅层。 N型掺杂含硅层的N型掺杂剂浓度高于至少一种含硅层。 对N型掺杂含硅层进行退火，以将N型掺杂含硅层的N型掺杂剂驱动到S / D区。

公开(公告)号：US20110254105A1

公开(公告)日：2011-10-20

申请号：US12761949

申请日：2010-04-16

Applicant: Chun-Fai Cheng ,  Ka-Hing Fung ,  Han-Ting Tsai ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Hsueh-Chang Sung ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

Inventor： Chun-Fai Cheng ,  Ka-Hing Fung ,  Han-Ting Tsai ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Hsueh-Chang Sung ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/28518 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device having a strained channel and a method of manufacture thereof is provided. The semiconductor device has a gate electrode formed over a channel recess. A first recess and a second recess formed on opposing sides of the gate electrode are filled with a stress-inducing material. The stress-inducing material extends into an area wherein source/drain extensions overlap an edge of the gate electrode. In an embodiment, sidewalls of the channel recess and/or the first and second recesses may be along {111} facet planes.

Abstract translation: 提供了具有应变通道的半导体器件及其制造方法。 半导体器件具有形成在通道凹槽上的栅电极。 形成在栅电极的相对侧上的第一凹部和第二凹部填充有应力诱导材料。 应力诱导材料延伸到其中源极/漏极延伸部与栅电极的边缘重叠的区域中。 在一个实施例中，通道凹槽和/或第一和第二凹部的侧壁可以沿{111}面平面。